Implementation method for digital channelized filter bank
A digital channelization and filter bank technology, applied in the field of communication, can solve the problems of consumption, huge hardware resources, waste of hardware resources, etc., and achieve the effects of low resource consumption, low calculation amount, and high adaptability
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[0056] Based on the digital channelization implementation technology of the present invention and the traditional digital channelization implementation technology, at the sampling rate f s =500MHz, frequency resolution △=15.7MHz, the sub-channels are evenly arranged and 50% overlapped, the comparison of hardware resource consumption.
[0057] Consider a single-frequency cosine input signal with a frequency of f=100MHz, assuming that the ADC at the receiving end is 18 bits, and the sampling rate is f s =500MHz, sampling period T s =1ns, the number of sampling points is D=16384.
[0058] The FPGA chip model used in this embodiment is: Kintex7-XC7K325T-FFG900.
[0059] The system working clock is: 125MHz.
[0060] In Embodiment 1, the hardware resource consumption based on the digital channelization realization technology of the present invention and the traditional digital channelization realization technology is measured by the resource consumption of the FPGA chip.
[0061...
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