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Dynamically patched high-performance on-chip cache fault-tolerant architecture

An on-chip cache and high-performance technology, which is applied to the generation of response errors and non-redundancy-based fault handling, etc., can solve the problems of ineffective response to intermittent bit failures and untimely processing, so as to ensure performance and performance fluctuations Small, guaranteed stable effect

Active Publication Date: 2018-06-19
BEIJING UNIV OF POSTS & TELECOMM
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  • Summary
  • Abstract
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  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

These methods are not processed in time, and cannot effectively deal with intermittent bit failures that occur randomly in time

Method used

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  • Dynamically patched high-performance on-chip cache fault-tolerant architecture
  • Dynamically patched high-performance on-chip cache fault-tolerant architecture
  • Dynamically patched high-performance on-chip cache fault-tolerant architecture

Examples

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Embodiment Construction

[0051] The following example specifically illustrates the sensitive mechanism algorithm:

[0052] Suppose an ordinary cache group with an associativity of 4 in the L1 cache, that is, a cache group contains four cache lines, the contents of the initial cache line, the reliability status identifier Line-Status of the cache line, and the corresponding counter values ​​are as follows Figure 8 shown. Each cache line is composed of a tag part and a data part. The tag part includes a flag flag bit, a subblock fault bitmap field, a cache disabled field, a data modified field, a subblock offset adjustment field, and a pointer field to a repair array. , to replace the flag bit, the data part uses 8-byte continuous space as a sub-block, and a cache group contains 8 sub-blocks. The content of the initial cache line is that the 3rd and 5th sub-blocks of the first cache line are faulty, the 5th and 6th sub-blocks of the second cache line are faulty, the 3rd sub-block of the third cache li...

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Abstract

The invention puts forward a dynamic repairing high-performance on-chip cache fault-tolerant framework, and can timely and efficiently process intermittent bit failure and permanent faults by low expenditure. Through a fault-sensitive replacement mechanism, new faults can be tolerated at any time, the cache is guaranteed to normally work, then, on the basis of a situation that a cache block is used and accessed, and a fault subblock is dynamically repaired to lighten an influence on the performance of the cache by faults.

Description

Technical field [0001] The patent of the present invention relates to a cache fault-tolerant architecture for repairing intermittent and permanent errors, especially a high-performance on-chip cache fault-tolerant architecture that can be dynamically repaired. Background technique [0002] Not only the permanent faults caused by missed detection and wear and aging will affect the reliability of the chips after leaving the factory, but also the gaps that are difficult to detect before leaving the factory, occur randomly in time, have a fixed position, last for a certain period, but are recoverable Bit failure also has a serious impact on the reliability of the chip after leaving the factory. Efficient error correction for transient faults Error detection codes also face the problem of high delay overhead when dealing with intermittent bit failures, and will weaken the handling of transient faults, causing multi-bit faults. Some cache architectures currently proposed to deal ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F11/07
CPCG06F11/073G06F11/0793
Inventor 黄智濒刘欣许翰元王珏满柯宇周锋
Owner BEIJING UNIV OF POSTS & TELECOMM
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