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Field-effect transistor and manufacturing method thereof

A technology of field-effect transistors and field regions, which is applied in the field of semiconductor chip manufacturing, can solve problems such as inaccurate test results and breakdown of thin gate oxide layers, and achieve accurate and reliable test results

Active Publication Date: 2019-11-08
FOUNDER MICROELECTRONICS INT
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Problems solved by technology

[0006] Aiming at the defects in the prior art, the present invention provides a field effect transistor and its manufacturing method, which are used to solve the problem that when the threshold voltage of the field transistor is tested, the voltage applied on the polysilicon is very likely to cause a thin gate oxide layer. breakdown, which makes the test results inaccurate

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  • Field-effect transistor and manufacturing method thereof
  • Field-effect transistor and manufacturing method thereof
  • Field-effect transistor and manufacturing method thereof

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Embodiment Construction

[0052] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0053] FIG. 2( i ) shows a schematic structural view of a field effect transistor provided by an embodiment of the present invention. As shown in FIG. 2( i ), the field effect transistor includes a first structure and a well region 0 .

[0054] The first structure includes a substrate 1, on which a plurality of field oxide layers 4 distributed at intervals are formed, and gate oxide layers 5 are formed in interval regions of the plurality of field oxide layers ...

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Abstract

The invention provides a field effect transistor. The field effect transistor comprises a first structure, wherein the first structure comprises a substrate, multiple field region oxide layers are formed on the substrate at intervals, grid oxide layers are formed at interval regions of the multiple field region oxide layers, source-drain regions are formed at sides of the grid oxide layers close to the substrate, a part of the multiple field region oxide layers is covered by a polysilicon layer, well regions are formed on the substrate at intervals, the well regions and the multiple field region oxide layers partially contact, the source-drain regions are in the well regions, and the well regions and a part of the polysilicon layer are oppositely arranged. The invention further provides a manufacturing method of the field effect transistor. The field effect transistor is advantaged in that the field region oxide layers are partially covered by the polysilicon layer, the well regions arranged opposite to the part of the polysilicon layer are made at periphery of the source-drain regions, breakdown of the grid oxide layers can be prevented when a threshold voltage of the field effect transistor is tested, and a test result is made to be reliable and accurate.

Description

technical field [0001] The invention relates to the field of semiconductor chip manufacturing, in particular to a field effect transistor and a manufacturing method. Background technique [0002] In the test structure of the chip, the structure of the field tube is quite special. It uses a thick field oxide layer as the gate oxide layer, so its threshold voltage will be relatively high, while the gate oxide layer of the conventional MOS tube in the chip is relatively thin. , At the junction of the field oxide layer and the MOS transistor gate oxide layer, when testing the threshold voltage of the field transistor, it is easy to cause breakdown of the MOS gate oxide layer, making the test results inaccurate. [0003] Conventional field tube structure and manufacturing process such as Figure 1(a) ~ Figure 1(h) . As shown in Figure 1(a), the growth of the thin oxide layer and silicon nitride layer; as shown in Figure 1(b), the etching of the silicon nitride layer; as shown in...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/78H01L21/336
CPCH01L29/66477H01L29/78
Inventor 马万里
Owner FOUNDER MICROELECTRONICS INT
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