Three-dimensional memory reading circuit and word line and bit line voltage configuration method

A three-dimensional storage and readout circuit technology, applied in the field of integrated circuits, can solve the problems of limiting three-dimensional memory readout speed and high power consumption, and achieve the effects of small read current, fast readout speed, and low readout power consumption

Active Publication Date: 2017-06-27
SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Higher read current not only leads to higher power consumption, but also limits the readout speed of 3D memory

Method used

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  • Three-dimensional memory reading circuit and word line and bit line voltage configuration method
  • Three-dimensional memory reading circuit and word line and bit line voltage configuration method
  • Three-dimensional memory reading circuit and word line and bit line voltage configuration method

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Embodiment Construction

[0065] Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

[0066] see Figure 5 ~ Figure 8 . It should be noted that the diagrams provided in this embodiment are only schematically illustrating the basic idea of ​​the present invention, and only the components related to the present invention are shown in the diagrams rather than the number, shape and shape of the components in actual implementation. Dimensional drawing, the type, quantity and proportion of each component can be changed arbi...

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Abstract

The invention provides a three-dimensional memory reading circuit and a word line and bit line voltage configuration method. The method comprises the following steps that: when a three-dimensional memory cell array is subjected to a reading operation, setting all bit lines in the three-dimensional memory cell array as reading unselect bit line voltage through a configuration module, setting all word lines in the three-dimensional memory cell array as reading unselect word line voltage; and after a pulse signal arrives, setting the bit line where a memory cell to be read is positioned as reading voltage Vread, and setting the word line where the memory cell to be read is positioned as 0V, wherein the reading unselect bit line voltage is between Vread / 2 and Vread, and the reading unselect word line voltage is between Vread / 2 and Vread. By use of the method, the voltage of two ends of a semi-gating unit on the bit line can be lowered, the chip of the three-dimensional memory has the advantages of lower power consumption, higher speed and no full-array electricity leakage during a reading operation, and the memory unit which is not selected on the selected word line still keeps semi-gating.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a three-dimensional memory readout circuit and a voltage configuration method for word lines and bit lines thereof. Background technique [0002] Three-dimensional integrated circuit (3D-IC) is one of the development directions of the integrated circuit industry. Three-dimensional integrated circuits can be divided into wafer-wafer stacking, die-wafer stacking and monolithic three-dimensional integrated circuits. Among them, the three-dimensional memory belonging to the monolithic three-dimensional integrated circuit has the fastest development. [0003] Integrated circuit memory is widely used in industrial and consumer electronics. According to whether the memory can be stored without power, it can be divided into volatile memory and non-volatile memory. Non-volatile memory includes flash memory (flash memory), magnetic memory (magnetoresistive random-access memo...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C7/12G11C8/08
CPCG11C7/12G11C8/08
Inventor 雷宇陈后鹏李喜王倩李晓云张琪宋志棠
Owner SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
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