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Precise low-speed low-input FPGA (field programmable gate array) delay estimation method

A delay estimation and fast technology, applied in computing, special data processing applications, instruments, etc., can solve problems such as neural network dependence

Inactive Publication Date: 2017-05-31
TIANJIN UNIV
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Problems solved by technology

However, this method is overly dependent on the neural network, and requires a large amount of data support to obtain high-precision delay estimation results, and requires a lot of time in the early stage

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  • Precise low-speed low-input FPGA (field programmable gate array) delay estimation method
  • Precise low-speed low-input FPGA (field programmable gate array) delay estimation method
  • Precise low-speed low-input FPGA (field programmable gate array) delay estimation method

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Embodiment Construction

[0061] The present invention provides an FPGA circuit delay estimation method based on a neural network fusion of architecture-level and transistor-level parameters, which can be combined with the architecture exploration process to accelerate the architecture exploration speed under the condition of ensuring accuracy. The specific technical scheme is as follows:

[0062] 1) Determine the fitting parameters α and effective mobility μ.

[0063] 2) Each sub-circuit in the FPGA is equivalent to an RC model, and combined with FPGA architecture parameters, the load capacitance of each type of transistor in each sub-circuit is determined.

[0064] 3) According to the determined fitting parameters ɑ, effective mobility μ, load capacitance and other parameters, a delay model is established for each sub-circuit in the FPGA, that is, the FPGA-macro delay model.

[0065] 4) Collect training data, analyze and normalize it.

[0066] 5) Combine the FPGA-macro delay model with the neural n...

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Abstract

The invention relates to the field of FPGA infrastructure optimization. In order to give comprehensive consideration on key parameters influencing circuit delay, allow coordinated exploration for variability of infrastructure-level parameters and transistor-level parameters in FGPA infrastructure design phase, embody and maintain inter-parameter physical significance, reduce training data quantity for a neural network and arrive at quick, precise, low-input delay estimation, the invention provides a precise low-speed low-input FPGA delay estimation method, comprising the steps of 1) determining fitting parameter Alpha and effective mobility Mu; 2) determining load capacitance of each transistor in each sub-circuit; 3) establishing an FPGA-macro delay model for each sub-circuit in the FGPA; 4) analyzing and normalizing; 5) solving weights Omega and Phi and number m of hidden neurons so that minimum training error Et and verification error Ev are achieved. The method of the invention is applied mainly in design and manufacture.

Description

technical field [0001] The invention relates to the field of FPGA architecture optimization, in particular to an FPGA delay calculation model. Specifically, it involves an accurate, fast and low-input FPGA delay estimation method. Background technique [0002] With the development of diverse applications, the FPGA architecture is constantly changing, and more and more time is spent on architecture exploration. The traditional method requires a lot of experiments to determine the FPGA architecture that meets the delay requirements. Architects need to use circuit simulation tools to measure the critical path delay under each FPGA architecture, and then use place and route tools to simulate the delay when the reference circuit is mapped to the FPGA architecture, and evaluate the architecture performance based on the results. In fact, it is impossible to explore all architectural designs with this experimental method, because it will take a lot of energy and time, especially i...

Claims

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Application Information

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IPC IPC(8): G06F17/50G06N3/063
CPCG06F30/3312G06N3/065
Inventor 钱涵晶刘强
Owner TIANJIN UNIV
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