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Hardware circular processing method and system of processor

A cycle processing and processor technology, applied in the direction of electrical digital data processing, instruments, machine execution devices, etc., can solve problems such as the impact of cycle efficiency

Active Publication Date: 2017-05-31
JIANGSU HONGYUN TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Although this method no longer uses additional judgment instructions and jump instructions, due to the delay in the program memory, it still needs additional waiting every time it jumps from the last instruction of the loop body to the first instruction of the loop body cycle to read the first instruction of the loop body
In this case, if there are fewer instructions in the loop body, these additional wait cycles will still have a serious impact on the efficiency of the loop

Method used

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  • Hardware circular processing method and system of processor
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  • Hardware circular processing method and system of processor

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Embodiment Construction

[0040] The preferred embodiments of the present invention will be described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described here are only used to illustrate and explain the present invention, and are not intended to limit the present invention. In any processor or DSP, the design of circular cache can be completed according to the method provided by this design.

[0041] figure 1 It is a pipeline architecture diagram according to the present invention. The processor or DSP shown in the figure includes sequentially cascaded program memory 100 , instruction fetch unit 101 , decoding unit 103 and execution unit 108 respectively corresponding to the four-stage pipeline F0~E0 of the processor or DSP. F0 is the first-stage pipeline for instruction reading, and the instruction fetch unit 101 issues a read request for the program memory 100 at this stage of the pipeline. F1 is the second-level pipeline for instruc...

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Abstract

The invention provides a hardware circular processing method and system of a processor. Circular buffering is increased in an original fetch unit; first N commands in a corresponding circular body are directly output to a subsequent decoding unit through the circular buffering, and a condition that an extra waiting period caused by the fact that the reading of data in a program memory is delayed during each skipping to a first command of the circular body from a final command of the circular body in a circular processing process is eliminated, so that zero-delaying skipping of hardware circulation is realized. The method provided by the invention has a simple design, and only one hardware circular buffering and a corresponding selection module need to be increased in an original system to realize the zero-delaying skipping of the hardware circulation. Furthermore, the access of the fetch unit on the program memory can also be reduced by utilizing the method so that the power consumption of the processor is reduced.

Description

technical field [0001] The invention relates to a hardware loop processing technology, in particular to a hardware loop processing technology improved for processor or DSP addressing level architecture. Background technique [0002] Loops are a very common type of program in a processor or DSP. In the prior art, common jump instructions are usually used in conjunction with general-purpose registers to implement loop processing. However, at the end of the loop body, this processing method needs to use additional instructions to judge whether the loop is over. If it is not over, it needs to use the jump instruction to jump to the first instruction of the loop body, which will bring inconvenience to the loop body. Less additional cycles. Especially in the case of loop nesting, the operation efficiency will be greatly impaired. [0003] In order to improve the execution efficiency of the loop, at present, some processors or DSPs start to use the hardware loop to process the l...

Claims

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Application Information

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IPC IPC(8): G06F9/30
CPCG06F9/30065G06F9/30069
Inventor 李炜陶建平韩景通
Owner JIANGSU HONGYUN TECH
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