Silicon wafer stage chip scale packaging structure and manufacturing method thereof

Abstract

The invention provides a silicon wafer stage chip scale packaging structure and a manufacturing method thereof. The silicon wafer stage chip scale packaging structure comprises a chip, a rewiring layer, a plurality of solder balls, a first plastic packaging layer and a second plastic packaging layer, wherein the rewiring layer covers the upper surface of the chip; the plurality of solder balls are formed on the upper surface of the rewiring layer and are electrically connected to the chip by the rewiring layer; the first plastic packaging layer surrounds the lower surface and side wall of the chip and the side wall of the rewiring layer; and the second plastic packaging layer is formed on the upper surface of the rewiring layer, surrounds each solder ball and is in seamless connection with the first plastic packaging layer, thereby forming the silicon wafer stage chip scale packaging structure surrounding the six surfaces of the chip. The silicon wafer stage chip scale packaging structure has the beneficial effects that the packaging protection surrounding the six surfaces of the chip is formed through seamless connection of the two plastic packaging layers, the buckling deformation of the packaging structure resulting from stress is effectively compensated, the packaging structure with the relatively big size can be prepared, and the packaging requirement of the large-sized chip is met.

Description

Technical field [0001] The present invention relates to the technical field of semiconductor packaging, in particular to a wafer-level chip-scale packaging structure and a preparation method thereof. Background technique [0002] Wafer Level Chip Scale Packaging (WLCSP), that is, wafer level chip packaging, is a low-cost mass production chip packaging technology, which is different from the traditional chip packaging method (first cutting and then sealing After packaging, increase the volume of the original chip by at least 20%), but directly perform overall packaging and testing on the entire wafer after the IC circuit is completed, and then cut into individual IC particles, which can be directly assembled, etc. The latter process is produced, so the packaged volume is equivalent to the original size of the IC bare chip, which is the smallest miniature surface mount device. WLCSP is a real chip size package. It is an improved and improved CSP (Chip Scale Package) based on BGA (...

AI Technical Summary

Problems solved by technology

[0006] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a wafer-level chip-scale packaging structure and its preparation method, which is used to solve the problem of the inability to prepare larger-sized packages due to package warping and deformation in the prior art. The wafer-level chip-scale packaging structure cannot meet the packaging requirements of large-size chips

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