An all-digital phase-locked loop and its phase-locked method

Abstract

The invention discloses an all digital phase locked loop and a phase locking method thereof. The phase locking method comprises the steps of calculating a first frequency difference based on an input frequency control word and a reference clock; filtering the first frequency difference based on a filtering coefficient to obtain a second frequency difference; calculating a frequency reference value based on the first frequency difference and the second frequency difference; determining an enabling control signal of a proportional integrator; carrying out proportion integral operation on the second frequency difference based on the enabling control signal and carrying out additive operation based an operation result and a frequency reference value to obtain a digital control oscillator control word; outputting a first clock corresponding to the digital control oscillator control word based on the digital control oscillator control word; applying the first clock to the all digital phase locked loop, and calculating the first frequency difference again based the first clock and the frequency control word; and when the first frequency difference calculated again is smaller than or equal to a preset threshold, locking the first clock. Through the way abovementioned, the phase locking speed can be speeded up efficiently and the phase locking calculation process can be simplified efficiently.

Description

technical field [0001] The invention belongs to the field of electronic technology, in particular to an all-digital phase-locked loop and a phase-locked method thereof. Background technique [0002] A phase-locked loop is a circuit that can synchronize the output signal with the input signal in frequency and phase, that is, after the system enters the locked state, the difference between the output signal and the input signal is zero, or remains constant. [0003] All digital phase-locked loop ADPLL (All Digital Phase-Locked Loop), that is, all the loop components are digitized, and the phase-locked loop is composed of a digital phase detector, a digital loop filter, and a digitally controlled oscillator, and the signals in the system are all Digital signal. Since some applications require the all-digital phase-locked loop to have a very short locking time, it is necessary to effectively accelerate the locking speed of the all-digital phase-locked loop. [0004] In the pri...

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Problems solved by technology

[0005] In summary, the method for accelerating the locking speed of the all-digital phase-locked loop in the prior art has the following disadvantages: the reduced locking time is limited, and cannot be applied to scenes with high requirements for phase-locking time; The calculation of the control word of the numerical control oscillator is too complicated

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