A Method for Checking the Functional Consistency of Standard Cells of Timing Library and Netlist Library

Abstract

A method for detecting functional consistency of standard units of a timing library and a netlist library includes the steps of acquiring function file of standard units of the timing library and the netlist library, acquiring functional attribute of the timing library to obtain a first boolean expression, acquiring functional description of the netlist library and converting the functional description into a second boolean expression, judging whether the first boolean expression and the second boolean expression are the same and then verifying functional consistency of the standard units of the timing library and the netlist library. According to the method for detecting functional consistency of standard units of timing library and netlist library, the functional description of Verilog is converted into the boolean expression, and the boolean expression is compared with the boolean expression defined by function attribute of the Timing Library; further, the classic BDD or SAT solver is utilized to judge whether the two boolean expressions are of equal value or not so as to verify the functional consistency of the standard units of the netlist library and the timing library effectively.

Description

technical field [0001] The invention relates to the field of computer-aided design of integrated circuits, in particular to a method for checking the consistency of standard unit functions of a timing library and a netlist library. Background technique [0002] With the development of chip technology, chip design is becoming more and more complex, and functional verification is very important in the entire design process. The traditional way to verify the function is through emulation, which is less efficient. [0003] In different files, the description forms of standard unit functions are completely different. The functional attributes in the timing library (Timing Library) are given by Boolean expressions, while in the netlist library (Verilog) file, the functions of standard cells can be described by the connection relationship of gate cells. and [0004] Therefore, proposing a new method for checking the consistency of the standard cell functions of the timing librar...

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Problems solved by technology

The traditional method of verifying functions is through simulation, which is less efficient

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