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Method for realizing high-order FIR filter based on FPGA

An implementation method and filter technology, applied in the direction of impedance network, digital technology network, electrical components, etc., can solve the problem of occupying logic units, etc., achieve the effect of reducing occupation, easy implementation, and ensuring real-time processing

Active Publication Date: 2017-03-29
XIDIAN UNIV
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Problems solved by technology

However, this method still occupies a large number of logic units in the process of completing polyphase filtering

Method used

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  • Method for realizing high-order FIR filter based on FPGA
  • Method for realizing high-order FIR filter based on FPGA
  • Method for realizing high-order FIR filter based on FPGA

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Embodiment Construction

[0027] The present invention will be described in further detail below in conjunction with the accompanying drawings and embodiments.

[0028] refer to figure 1 with figure 2 , the present invention comprises the following steps:

[0029] Step 1, select the prototype filter parameters.

[0030] The parameters of the prototype filter are mainly selected according to the performance requirements of the voice signal processing system, the image signal processing system and the digital channelizer system, and the present embodiment selects the prototype filter parameters according to the performance requirements of the digital channelizer system, and the digital channelizer system The performance requirements are as follows:

[0031] (1). The channel bandwidth is 160MHz, which is divided into 64 sub-channels;

[0032] (2). The effective bandwidth in the channel is 120MHz, including 48 sub-channels;

[0033] (3). The sub-channel bandwidth is 2.5MHz;

[0034] (4). The guard i...

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Abstract

The invention provides a method for realizing a high-order FIR filter based on an FPGA, used for solving the technical problem of excessive occupation of the high-order FIR filter to logic units in the FPGA in the existing method for realizing high-order FIR multiphase filtering. The method comprises the following steps: selecting parameters of a prototype filter; designing the prototype filter h (n); performing multiphase decomposition on the prototype filter h (n) to obtain multiphase filters; performing module division on each multiphase filter; storing coefficients of the multiphase filters in a module ROM; reading the coefficients of the multiphase filters in the module ROM; caching and reading input data by read-write enable, a write address control signal and a read address control signal of a module RAM obtained by system clock control; and performing multiplication and addition operations on the coefficients of the multiphase filters and the input data by using a multiplication accumulation module, and outputting an operation result. The method provided by the invention is little in occupation of the logic units in the FPGA, simple, efficient and is easy to realize.

Description

technical field [0001] The invention belongs to the technical field of digital signal processing, and relates to a method for a high-order FIR digital filter, in particular to a method for realizing an FPGA-based high-order FIR filter, which can be used for signal filtering in digital channelization. Background technique [0002] The high-performance digital channelizer can effectively improve the flexibility and extensibility of the satellite transponder, complete the signal exchange between each sub-channel in the communication link, and greatly improve the bit error performance of the system, thus becoming a broadband satellite mobile communication application urgent needs of the field. However, each sub-channel signal is easily interfered by noise and other sub-channel signals during transmission, which will lead to a sharp deterioration in the performance of the entire communication system. How to effectively filter out noise and out-of-band interference and restore eac...

Claims

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Application Information

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IPC IPC(8): H03H17/00
CPCH03H17/00H03H2017/0081
Inventor 田斌王召杰易克初孙林海黄俊桦
Owner XIDIAN UNIV
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