Method and system for external download of DSP (digital signal processor) program and FPGA (field programmable gate array) program

Abstract

The invention provides a method and a system for external download of a DSP (digital signal processor) program and an FPGA (field programmable gate array) program. The system comprises a 1553B interface circuit, a DSP processor, a DSP storage unit, a watchdog circuit, an FPGA and an FPGA storage unit. The 1553B interface circuit is connected with the DSP processor through an EMIFA (external memory interface A), the watchdog circuit is connected with the DSP processor through a GPIO (general purpose input / output) interface, and the DSP storage unit is connected with the DSP processor through an EMIFB (external memory interface B) and a GPIO interface. The FPGA storage unit is connected with the DSP processor through a McBsp interface, the DSP processor is connected with the FPGA through a GPIO interface, and the FPGA storage unit is connected with the FPGA through a serial bus. The method and the system for external download of the DSP program and the FPGA program have the advantage that practicability, reliability and real-time performance of the system for external download can be improved.

Description

technical field [0001] The invention relates to the technical field of embedded devices, in particular to an external download system and method for DSP programs and FPGA programs. Background technique [0002] With the continuous development of electronic technology and the continuous improvement of user needs, it is necessary to frequently update the embedded device programs that have been put into use. Generally, software program updates based on DSP and FPGA are implemented through JTAG interface operations in the development environment. . Although the method based on the JTAG interface is easy to operate and debug, it is often limited by space and transmission distance. Therefore, it is an urgent need to develop efficient and convenient upgrading technology. [0003] In the prior art, an online upgrade suitable for TMS320C2000 series DSPs to implement program updates based on serial port communication is disclosed. However, its disadvantages are: the DSP program stor...

AI Technical Summary

Problems solved by technology

Although the method based on the JTAG interface is easy to operate and debug, it is often limited by space and transmission distance. Therefore, it is an urgent need to develop efficient and convenient upgrade technology

[0003] In the prior art, an online upgrade suitable for TMS320C2000 series DSPs to implement program updates based on serial port communication is disclosed. However, its disadvantages are: the DSP program storage FLASH is located in the DSP chip, and the capacity is small, which cannot meet the requirements of digital data with high complexity. The need for signal processing has certain limitations in use; at the same time, it does not adopt a working status monitoring mechanism, does not have a self-recovery function, and its reliability and versatility are not perfect.

[0004] The prior art also discloses an online upgrade method, which improves the reliability of software upgrades by means of FLASH partition storage, divides FLASH into two different partitions, the startup code area and the product program area, and the online upgrade software stored in the startup code area , through the RS422 / RS232 / CAN interface to read and write the product program area to realize the boot and start of the product software, but the disadvantage is that the partition storage method does not expand the storage space, and the startup code area and the product program area share the original FLASH When the product program area has a lot of data storage requirements, it may not be able to meet the needs of data storage, and the scalability is poor; moreover, the online reload function is not implemented, and the loading of the product program area code needs to be powered off and restarted, real-time and flexible The performance is poor; similarly, the design does not adopt the working status monitoring mechanism, does not have the self-recovery function, and the reliability and versatility are not perfect

[0005] In addition, the prior art also discloses the use of CPLD or DSP as the configuration master to realize the FPGA online upgrade and dynamic loading based on the FLASH process. The control is complicated and the reliability is poor; in the case of large FPGA program files, there are great limitations in use and poor versatility; similarly, the design does not adopt a working status monitoring mechanism and does not have a self-recovery function

[0006] In summary, none of the prior art has proposed a 1553B bus-based, compatible with DSP and FPGA two embedded processor online upgrades, with online reloading function and working status monitoring function with high reliability and good general purpose. Sexual external download system

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