Method for evaluating single-particle multi-transient soft error sensitivity of combinational logic circuit considering layout information

Abstract

The invention provides a method for evaluating single-particle multi-transient soft error sensitivity of a combinational logic circuit considering layout information, and relates to a soft error sensitivity evaluation technique of the combinational logic circuit, which aims at solving the problem of failure to effectively evaluate the single-particle multi-transient soft error sensitivity in the existing soft error evaluation method of the combinational logic circuit. The method comprises the following steps of S1, according to the layout information, extracting an effective sensitive body, and performing Geant4 Monte-Carlo simulation; S2, generating a 'golden' netlist file, and calling a quick SPICE simulation tool to simulate; S3, generating an error injection netlist, and calling the quick SPICE simulation tool to simulate; S4, according to the obtained logic states of the output end of the combinational logic circuit in steps 2 and 3, obtaining the failure rate of the combinational logic circuit, and according to the failure rate, evaluating the single-particle multi-transient soft error sensitivity of the combinational logic circuit. The method is suitable for evaluating the soft error sensitivity of the combinational logic circuit.

Description

technical field [0001] The present invention relates to soft error susceptibility assessment techniques for combinational logic circuits. Background technique [0002] With the continuous development of integrated circuit technology, soft errors caused by single event events have become the main threat to the reliability of integrated circuits. The increase in transistor density and the reduction of critical charges have made low-energy protons and muons, which are insignificant on the micrometer scale, even a potential threat to nanoscale integrated circuits. When a particle with a certain energy hits the reverse-biased P-N junction in the transistor, a high-density electron-hole pair will be generated on the track it passes through due to direct ionization or nuclear reaction. Under the action, it will be absorbed by the drain of the transistor based on the effect of diffusion and drift. If this process acts on storage devices such as SRAM or registers, the logic state o...

AI Technical Summary

Problems solved by technology

[0004] The purpose of the present invention is to solve the problem that the existing combinational logic circuit soft error evaluation method cannot effectively evaluate the soft error sensitivity of single event multiple transient, so as to provide a combinational logic circuit that considers the layout information of the single event multiple transient State Soft Error Sensitivity Evaluation Method

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