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Calibration algorithm applied to time-interleaved analog-to-digital converter

An analog-to-digital converter and time interleaving technology, applied in the direction of analog-to-digital converter, analog/digital conversion calibration/test, etc., can solve the problems of poor calibration effect and high logic resource consumption, saving loss, reducing complexity, The effect of real-time calibration

Inactive Publication Date: 2017-02-08
苏州迅芯微电子有限公司
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Problems solved by technology

[0004] The purpose of the present invention is to provide a calibration algorithm applied to time-interleaved analog-to-digital converters to solve the problems of high logic resource consumption and poor calibration effect of off-chip calibration algorithms in the prior art

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Embodiment Construction

[0033] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of embodiments of the present invention, but not all embodiments.

[0034] The invention discloses a calibration algorithm applied to a time-interleaved analog-to-digital converter, which mainly adopts off-chip calibration technology, such as figure 1 shown, including the following steps:

[0035] Step S101, sampling the analog signal through the multi-channel analog-to-digital converter ADC;

[0036] Specifically, in this embodiment, as figure 2 As shown, the multi-channel sub-analog-to-digital converter ADC of TI-ADC can be used 1 、ADC 2 and ADC m Single-frequency sine waves are sampled separately, but in th...

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Abstract

The invention provides a calibration algorithm applied to a time-interleaved analog-to-digital converter, comprising the following steps: sampling analog signals through multiple sub analog-to-digital converters ADC; processing digital signals obtained after sampling through a field-programmable gate array (FPGA for short), and calculating error values; carrying out real-time feedback regulation according to the calculated error values; and repeating the steps until the error values converge to fixed values. Statistical analysis and feedback regulation are used in the algorithm. Sampling data is processed by the FPGA in real time to get three error values (offset mismatch error, gain mismatch errors and sampling time interval mismatch error), then, real-time feedback regulation is carried out in real time according to the error values until the error values converge, and finally, calibration of the time-interleaved ADC is finished. Therefore, the complexity of the calibration algorithm is reduced effectively, real-time calibration is realized, and hardware resource depletion is reduced.

Description

technical field [0001] The invention relates to the technical field of integrated circuit data converter chip design, in particular to a calibration algorithm applied to a time-interleaved analog-to-digital converter. Background technique [0002] The basic structure of Time-interleaved Analog-to-Digital Converter (TI-ADC for short) is as follows: figure 1 As shown in the middle part, it combines multiple sub-ADCs to achieve uniform and alternate sampling, and doubles the overall sampling rate of the ADC without increasing the sampling rate of the sub-ADCs. However, in an actual circuit, there may be a mismatch in the performance of each sub-ADC, and there may be a time deviation in sampling, resulting in serious mismatch errors, which will seriously affect the overall performance index of the time-interleaved ADC. In order to reduce the impact of mismatch errors on time-interleaved ADC, calibration technology is introduced. Generally, calibration technology is divided into...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M1/10H03M1/12
CPCH03M1/10H03M1/12
Inventor 周磊陈莲
Owner 苏州迅芯微电子有限公司
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