A chemical mechanical polishing method for an interlayer dielectric layer and its device and electronic device

Abstract

A chemical mechanical polishing method of an interlayer dielectric layer, and a device and electronic equipment with the interlayer dielectric layer are provided; the method comprises: providing a front-end device comprising a semiconductor substrate and first and second gates positioned on the semiconductor substrate, wherein the width of the first gate is greater than that of the second gate and a hard mask layer is formed on the first gate; forming an etching stop layer on the first gate, the second gate and the semiconductor substrate; forming an interlayer dielectric layer on the etching stop layer; executing first chemical mechanical polishing until the surface of the etching stop layer above the first gate; forming, on the interlayer dielectric layer, a mask layer that exposes the etching stop layer above the first gate; performing etching process to remove the etching stop layer and the hard mask layer not covered by the mask layer; executing second chemical mechanical polishing until the surface of the etching stop layer above the second gate. The method according to the invention enables silicon nitride residue and disc dents on gates to be effectively avoided, the interlayer dielectric layer that is polished has good surface flatness, and the properties and yield of the device are increased.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a chemical mechanical polishing method for an interlayer dielectric layer, a device and an electronic device thereof. Background technique [0002] Chemical mechanical polishing (CMP) is a processing technology that combines chemical corrosion and mechanical removal, and is mainly used for the planarization of silicon wafers in the semiconductor industry. The effect of surface planarization by CMP is greatly improved compared with the effect of surface planarization by traditional planarization technology, so CMP has become a key planarization technology in the semiconductor industry. [0003] At present, when the size of the semiconductor device is reduced to 28nm or below, the fabrication method of the interlayer dielectric layer (ILD) between polysilicon gates is mostly carried out by fixed abrasive (FA) CMP. At the 28nm scale, the thickness of the hard mask silicon ni...

AI Technical Summary

Problems solved by technology

It can be seen from the figure that after the stress proximity technique (SPT), ILDCMP using the FA method can obtain less silicon nitride residues and smaller dish-shaped depressions, and better flatness; while ILDCMP using the abrasive slurry There will be more silicon nitride residue and larger dishing, thicker SiN residue thickness on the wider gate area, and poor planarity

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