Method for preventing growth of redundant SiGe in shoulder part of grid

Abstract

The invention provides a method for preventing growth of redundant SiGe in the shoulder part of a grid. The method comprises that a semiconductor substrate including a PMOS area and an NMOS area is provided, an NMOS grid structure and a PMOS grid structure are formed on the substrate, first hard masks are formed on the NMOS grid structure and the PMOS grid structure respectively, and first sidewalls are formed in the sidewalls of the NMOS grid structure and the PMOS grid structure respectively; a first material layer is formed on the PMOS area and the NMOS area; a second material layer is formed on the first material layer; the second material layer is etched to form second sidewalls in the sidewalls of the NMOS grid structure and the PMOS grid structure respectively; a second hard mask layer is formed on the PMOS area and the NMOS area; the second hard mask layer is patterned to remain only part of hard mask layer on the NMOS area, and the part of hard mask layer is etched to form a SiGe source-drain U-shaped trench in the PMOS area; and the SiGe source-drain U-shaped trench is etched for form a similarly E-shaped trench, and epitaxial growth of SiGe in the PMOS source-drain area is executed.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, and more specifically, the invention relates to a method for preventing excess SiGe from growing on gate shoulders, which is mainly used in 28nm integrated circuits, especially in the manufacture of SRAM technology. Background technique [0002] When the integrated circuit technology develops to 28 nanometers and below, the growth and control of SiGe presents a huge challenge, especially the limitation of the process window. In particular, the requirement for the thickness of the first sidewall for ion implantation in the PMOS region should not be too thick. However, in reality, the cleaning process before SiGe U-etch, tetramethylammonium hydroxide (TMAH) etch and SiGe growth causes the loss of gate hard mask and spacer, resulting in the spacer covering the gate. The thickness of the film is limited. When SiGe is grown, excess SiGe may grow and form defects. The size and direction of t...

AI Technical Summary

Problems solved by technology

However, in reality, the cleaning process before SiGe U-etch, tetramethylammonium hydroxide (TMAH) etch and SiGe growth causes the loss of gate hard mask and spacer, resulting in the spacer covering the gate. The thickness of the film is limited. When growing SiGe, excess SiGe may grow and form defects. The size and direction of growth cannot be controlled, which will affect the subsequent process and even cause SRAM to have no function.

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