Array substrate, manufacturing method therefor, and liquid crystal display panel

Abstract

The invention provides an array substrate, and the array substrate comprises a glass substrate, a photoresist layer, a first metal layer, a dielectric layer, a buffering layer and a second metal layer, wherein the glass substrate, the photoresist layer, the first metal layer, the dielectric layer, the buffering layer and the second metal layer are sequentially stacked. A side, close to the first metal layer, of the photoresist layer is provided with a plurality of bulged structures, and the first metal layer covers the bulged structures. The first metal layer, the dielectric layer, the buffering layer and the second metal layer has the same shape as the bulged structures. According to the invention, the photoresist layer is provided with the bulged structures, thereby enabling the firs metal layer, the dielectric layer, the buffering layer and the second metal layer on the bulged structures to be corrugated, increasing the opposite area of the first and second metal layers, increasing the equivalent capacitance, facilitating the reduction of a space occupied by an equivalent capacitor, and achieving a narrow frame design. A manufacturing method for the array substrate can reduce the space occupied by the equivalent capacitor, and achieves the narrow frame design.

Description

technical field [0001] The invention relates to the technical field of displays, in particular to an array substrate, a manufacturing method thereof, and a liquid crystal display panel. Background technique [0002] In the prior art, usually in the array process stage of the liquid crystal display panel, the gate driver circuit is manufactured on the array substrate by using GOA (Gate Driver OnArray) technology, so as to realize the progressive scan driving of the gate lines. Compared with traditional COF (Chip On Flex / Film, chip-on-film) technology and COG (Chip OnGlass, chip directly bonded to glass) technology, GOA technology can reduce manufacturing costs. The main feature of GOA technology is that it relies on continuous triggering of GOA units. Realize the shift register function, save the bonding area of ​​the gate integrated circuit (Gate IC) and the Fan-out wiring space, and realize the design of the narrow frame. [0003] In GOA circuit design, TFT (Thin Film Tran...

AI Technical Summary

Problems solved by technology

However, the Boost capacitor usually needs to reach the picofarad (pF) level to make the GOA circuit work effectively. For example, the capacitance area of ​​a 10pF Boost capacitor usually needs to reach 0.1mm 2 , for a higher resolution LCD (Liquid Crystal Display, liquid crystal display) panel, the size of the TFT and Boost capacitor needs to be further increased

In other words, the area occupied by TFT and Boost capacitors is relatively large, which brings great difficulties to the design of narrow-frame, high-resolution GOA circuits

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