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Manufacturing method of p-channel flash memory

A manufacturing method and memory technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electric solid-state devices, etc., can solve the problems of poor durability and achieve good durability, quantity reduction, and slow reduction of working threshold

Active Publication Date: 2019-07-16
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0013] The purpose of this application is to provide a manufacturing method of P-channel flash memory to solve the problem of poor durability of P-channel flash memory in the prior art

Method used

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  • Manufacturing method of p-channel flash memory
  • Manufacturing method of p-channel flash memory
  • Manufacturing method of p-channel flash memory

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Embodiment Construction

[0041] It should be pointed out that the following detailed description is exemplary and intended to provide further explanation to the present application. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.

[0042] It should be noted that the terminology used here is only for describing specific implementations, and is not intended to limit the exemplary implementations according to the present application. As used herein, unless the context clearly dictates otherwise, the singular is intended to include the plural, and it should also be understood that when the terms "comprising" and / or "comprising" are used in this specification, they mean There are features, steps, operations, means, components and / or combinations thereof.

[0043] For the convenience of description, spatially relative terms may be used here, such as "on ...", "over .....

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Abstract

The invention provides a manufacture method of a P channel flash memory. The manufacture method includes the following steps that: step S1, a storage structure and a selection gate structure which are isolated from each other are arranged on an N type semiconductor substrate, wherein the storage structure comprises a first dielectric layer, a floating gate, a second dielectric layer and a control gate which are sequentially far away from the N type semiconductor substrate and are arranged in a stacked manner; step S2, ion implantation is performed on the N type semiconductor substrate, so that a drain electrode extension region can be formed, wherein the drain electrode extension region is located in the N type semiconductor substrate at the first side of the selection gate structure; step S3, side walls are formed on the side surfaces of the storage structure and the selection gate structure; and step S4, ion implantation is performed on the N type semiconductor substrate, so that a drain electrode can be formed in the drain electrode extension region, and a source electrode can be formed in the N type semiconductor substrate at the second side of the storage structure, and a P region is formed in the N type semiconductor substrate between the first side of the storage structure and the second side of the selection gate structure. With the method adopted, the reduction of the working threshold value of the P channel flash memory can be slowed, and the P channel flash memory has high durability.

Description

technical field [0001] The present application relates to the technical field of semiconductor manufacturing, and in particular, to a method for manufacturing a P-channel flash memory. Background technique [0002] Flash memory is a type of non-volatile memory in which data is retained even after power to the device is removed, thus allowing data to be written, read, and erased multiple times. Since the flash memory has the advantages mentioned above, it has been widely used in personal computers and electronic devices. [0003] Such as figure 1 The traditional flash memory shown includes an N-type semiconductor substrate 100', a storage structure 200', a spacer 600', a drain 401' and a source 701', and the storage structure 200' includes sequentially arranged on the N-type semiconductor substrate The tunnel oxide layer 201 ′, the floating gate 202 ′, the gate dielectric layer 203 ′, the control gate 204 ′ on the surface, and the sidewall 600 ′ are arranged on the sidewall...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/11521H01L21/265
Inventor 叶晓金凤吉
Owner SEMICON MFG INT (SHANGHAI) CORP
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