Simulation hardware accelerator based on PLI (Private Line Interface)-VPI (Virtual Path Identifier) and special acceleration hardware

Abstract

The invention designs a simulation hardware accelerator based on acceleration hardware, which is constructed by employing an advanced CPU (Central Processing Unit) and concurrency of a large number of logical operation processing unit system structures on a special simulation acceleration processor (VPU) based on a PCIE (Peripheral Component Interface Express) high-speed interconnection bus and combining a concurrent processing hardware and software technology through seamless connection of simulation tool software of an industrial PLI / VPI interface protocol standard and an intra-industry standard. The accelerator comprises the CPU, a main board chipset, a memory, a hard disk, a compact disc read-only memory driver, a power supply, an extended port and a special hardware acceleration card PCIE, wherein the CPU comprises a 4-way CPU; the special hardware acceleration card includes a 4-way special hardware acceleration card, an SOC (System on Chip) calculation array is formed. According to the simulation hardware accelerator designed by the invention, the simulation efficiency is improved, the simulation complexity is reduced, the simulation time is shortened, and a key link is finished for design of an integrated circuit system.

Description

technical field [0001] The invention belongs to the technical field of simulation verification accelerators in integrated circuit design, and relates to a simulation hardware accelerator based on PLI / VPI and special acceleration hardware. Background technique [0002] In the design of deep submicron VLSI, the simulation verification task is not only an indispensable task, but also gradually becomes the bottleneck of the overall SoC chip design project as the geometric progression of the chip scale increases, and simulation requires The design verification engineer builds a test platform for the design project according to the chip function list, so as to provide observable output responses. According to these output response information, the engineer can judge whether the circuit meets the expected functions. Due to the complexity of the current SoC chip functions, a large number of iterative simulation regression test vectors are required to ensure the correct test coverage...

AI Technical Summary

Problems solved by technology

[0004] The problem to be solved by the present invention is to design a simulation hardware accelerator based on PLI / VPI and special acceleration hardware, improve simulation efficiency, reduce simulation complexity, and shorten simulation time

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