Eureka AIR delivers breakthrough ideas for toughest innovation challenges, trusted by R&D personnel around the world.

Heterogeneous multi-core processor for tabu search scheduling algorithm

A technology of multi-core processors and scheduling algorithms, applied in electrical digital data processing, instruments, calculations, etc., can solve problems such as energy waste, high performance, loss, etc., and achieve the effect of reducing the number of sampling times and thread migration times

Active Publication Date: 2016-07-27
HUNAN UNIV
View PDF1 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] If the scheduler ignores unforeseen heterogeneous changes in the core, it will cause a large performance loss; if the global power manager ignores this change, it will cause unacceptable energy waste

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Heterogeneous multi-core processor for tabu search scheduling algorithm
  • Heterogeneous multi-core processor for tabu search scheduling algorithm
  • Heterogeneous multi-core processor for tabu search scheduling algorithm

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0025] The present invention will be further described below in conjunction with the accompanying drawings and preferred embodiments.

[0026] The heterogeneous multi-core processor system is realized by using multiple single cores and an upper framework. The framework structure is as follows: figure 1 shown. The bottom layer of the framework is many single cores. During the exploration cycle, the framework samples each thread, and a single core collects the performance and energy consumption parameters of the threads running on it, and then passes these parameters to the upper framework. The main functions of the upper framework include thread scheduling, resource coordination management and performance statistics. The upper-layer framework is responsible for specifying the assignment scheme for each thread in the exploration cycle of each power management time slice. It will collect and analyze the sampling data of each core, and then use the scheduling algorithm to genera...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses a heterogeneous multi-core processor for a tabu search scheduling algorithm. The heterogeneous multi-core processor with at least eight cores is applied to an upper-layer framework for thread scheduling, resource synergy management and performance statistics, and used for recording a tabu list of an optimal scheduling scheme of two threads on two processors, enhancing the system performance of the heterogeneous multi-core processor and saving energy. Through adoption of the heterogeneous multi-core processor for the tabu search scheduling algorithm, the thread migration times and sampling times are reduced effectively; the problem that only time and energy effective rate are considered in a conventional design is solved; the overall performance of a processor chip is improved effectively; and the energy consumption is lowered.

Description

technical field [0001] The invention relates to the field of processor chips, in particular to a heterogeneous multi-core processor with a tabu search scheduling algorithm. Background technique [0002] With the continuous development of the semiconductor industry, the number of transistors placed on the wafer continues to increase, and the multi-processor architecture has gradually become the mainstream chip structure. Compared with designing and manufacturing higher frequency and more complex single processors, the industry tends to integrate multiple processor cores on the same chip to obtain performance improvements. On-chip multiprocessor chips (ChipMultiprocessor, CMP) have been widely used in high-performance computing, desktop systems, and embedded systems. [0003] Power consumption is one of the main design constraints and performance constraints of many-core chips at present and in the future. If the power level of a single processor core in a many-core chip is ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/48G06F9/50
CPCG06F9/4881G06F9/4893G06F9/5027G06F2209/508Y02D10/00
Inventor 刘彦马啸啸赵一宏李永伟李洪贵
Owner HUNAN UNIV
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com