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Multi-core processor supporting cache consistency, reading and writing methods and apparatuses as well as device

A multi-core processor and consistent technology, applied in the field of multi-core processors, can solve the problems of prolonged access to shared cache, affecting data access performance, and the cache directory of multi-core processors occupying cache space, etc.

Active Publication Date: 2016-07-06
ALIBABA GRP HLDG LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0010] The present application provides a multi-core processor supporting cache coherence, so as to solve the problem that the cache directory of the existing multi-core processor occupies cache space, affects data access performance, and prolongs access to shared cache

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  • Multi-core processor supporting cache consistency, reading and writing methods and apparatuses as well as device
  • Multi-core processor supporting cache consistency, reading and writing methods and apparatuses as well as device
  • Multi-core processor supporting cache consistency, reading and writing methods and apparatuses as well as device

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Embodiment Construction

[0115] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, the present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar promotions without violating the connotation of the present application. Therefore, the present application is not limited by the specific implementation disclosed below.

[0116] In this application, a multi-core processor supporting cache coherence, a data reading method and device based on the multi-core processor, and a data writing method and device based on the multi-core processor are respectively provided , A memory allocation method and apparatus based on the multi-core processor, and a device. The embodiments of the present application will be described in detail below one by one.

[0117] Please refer to figure 2 , which is a schematic diagram of the architecture...

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Abstract

The invention discloses a multi-core processor supporting cache consistency, a data reading method and apparatus based on the multi-core processor, a data writing method and apparatus based on the multi-core processor, a memory allocation method and apparatus based on the multi-core processor, and a device. The multi-core processor supporting cache consistency comprises a plurality of processor cores and local caches corresponding to the processor cores respectively, wherein the local caches of different processor cores are used for caching data in memory spaces of different address ranges respectively; and each processor core accesses the data in the local caches of other processor cores through an interconnection bus. According to the technical scheme provided by the invention, a new thought of removing a cache directory and shared caches from a conventional multi-core processor framework is provided, so that the cache consistency is realized, private caches are shared, and the overall performance of the processor is improved while the conflicts between the private caches and the shared caches are eliminated.

Description

technical field [0001] The present application relates to the field of multi-core processors, in particular to a multi-core processor supporting cache coherence. The present application also provides a data reading method and device based on the multi-core processor, a data writing method and device based on the multi-core processor, and a memory allocation method and device based on the multi-core processor. , a device, and another multicore processor that supports cache coherence. Background technique [0002] In the process of computer technology development, the access speed of the main memory (that is, the so-called physical memory or memory) has always been much slower than the operation speed of the central processing unit, so that the high-speed processing capability of the central processing unit (CPU) cannot be obtained. fully use. In order to alleviate the contradiction between the speed mismatch between the CPU and the main memory, a cache memory (cache, usuall...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/08
CPCG06F12/084G06F2212/1028G06F12/0815G06F12/0811G06F2212/283G06F2212/621Y02D10/00
Inventor 马凌周伟张磊
Owner ALIBABA GRP HLDG LTD
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