Method of forming semiconductor device

Abstract

A method for forming a semiconductor device, comprising: providing a semiconductor substrate, forming a gate structure on the semiconductor substrate, the gate structure comprising a gate dielectric layer, a gate electrode layer positioned on the gate dielectric layer, and a gate electrode layer positioned on the gate dielectric layer A hard mask layer on the layer; an oxide layer is formed on the sidewall surface of the gate electrode layer; the hard mask layer is etched to remove a part of the hard mask layer to expose the shoulder of the gate electrode layer part; forming a sidewall material layer covering the surface of the semiconductor substrate, the surface of the gate structure, and the shoulder of the gate electrode layer, and the part of the sidewall material layer in contact with the shoulder at least partially utilizes the shoulder of the shoulder material formation; and removing the sidewall material layer located on the surface of the semiconductor substrate and the top surface of the gate structure by a dry etching process, and the sidewall material layer located on the sidewall surface of the gate structure forms a sidewall. The method for forming a semiconductor device of the present invention can effectively improve the formation of gate germanium silicon residual defects.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a method for forming a semiconductor device. Background technique [0002] With the rapid development of VLSI technology, the size of MOSFET devices is continuously reduced, usually including the reduction of the channel length of MOSFET devices, the thinning of gate oxide layer thickness, etc., to obtain faster device speed. However, with the development of VLSI technology to the ultra-deep sub-micron level, especially when the technology node is 90 nanometers and below, the reduction of the channel length will bring a series of problems. In order to control the short channel effect, the channel will be doped Impurities with a higher concentration will reduce the mobility of carriers, resulting in a decrease in device performance. It is difficult to simply reduce the size of the device to meet the development of large-scale integrated circuit technology. Therefore, stress engineer...

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Problems solved by technology

[0004] However, in the prior art, after the embedded silicon germanium source and drain are formed, there are silicon germanium residues in the gate.

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