A parallel scrambling device and parallel scrambling method
A clock cycle, generator technology, applied in the direction of logic circuits with logic functions, multiplexing code generation, electrical components, etc., can solve the problem of increasing equipment cost and design difficulty, less scrambling code bits, and excessive equipment work capacity requirements. higher question
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[0102] In order to make the purpose, technical solutions and advantages of the application clearer, the application will be further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only some of the embodiments of the application, not all of them. . Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of this application.
[0103] The embodiments of the present application will be further described in detail below in conjunction with the accompanying drawings.
[0104] Such as figure 1 As shown, it is a schematic diagram of the parallel scrambling device provided in the embodiment of the present application, including:
[0105] Parallel scrambling code generator 101, selection judge 102, exclusive OR operator 103;
[0106] The output end of the parallel scrambling code generator 101 ...
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