esd device, manufacturing method of esd device and eeprom

Abstract

The invention discloses an ESD device, a manufacturing method of the ESD device and an EEPROM. The ESD device comprises a semiconductor base body, a trap arranged in the semiconductor base body, a grid electrode structure arranged on the surface of the trap, a source electrode, a drain electrode and an ion injection region. The source electrode is arranged in the trap and on one side of the grid electrode structure. The drain electrode is arranged in the trap and on the other side of the grid electrode structure. The conduction types of the source electrode and of the drain electrode are opposite to the conduction type of the trap. The ion injection region is arranged in the drain electrode. The conduction type of the ion injection region is opposite to that of the drain electrode. Via the ion injection region, the doping density in the drain electrode can be reduced, so probability of impact ionization of charge carriers and neutral atoms between the drain electrode and the semiconductor base body is increased, thereby reducing backward voltage required by avalanche breakdown between the drain electrode and the semiconductor base body, and further reducing starting voltage of the ESD device.

Description

technical field [0001] The present application relates to the technical field of semiconductor integrated circuits, and in particular, relates to an ESD device, a manufacturing method of the ESD device, and an EEPROM. Background technique [0002] The entire life cycle of semiconductor integrated circuits from growth to packaging and testing will face various unpredictable electrostatic environments, which will easily introduce static electricity into semiconductor integrated circuits, which will cause electrostatic damage to semiconductor integrated circuits. Therefore, the design of semiconductor integrated circuits not only needs to meet functional requirements, but also has a certain electrostatic protection capability. Especially for EEPROM (Electrically Erasable Programmable Read-Only Memory), since the EEPROM contains many high-voltage devices, it needs to have a certain electrostatic protection capability. [0003] At present, ESD devices are usually designed in sem...

AI Technical Summary

Problems solved by technology

[0005] However, the turn-on voltage of the above-mentioned ESD device (referring to the absolute value of turn-on voltage here) is relatively high, so that it cannot meet the needs of semiconductor integrated circuits for electrostatic protection.

For example, HV 5V PMOS devices are usually used as ESD devices in existing EEPRPMs, and the turn-on voltage of HV 5V PMOS devices is usually -13V, while the design turn-on voltage of EEPRPM is -10V, which can no longer meet the needs of EEPRPM for electrostatic protection capabilities

Images