esd device, manufacturing method of esd device and eeprom

Abstract

This application discloses an ESD device, a manufacturing method of the ESD device and an EEPROM. Wherein, the ESD device includes: a semiconductor base and a well disposed in the semiconductor base; a gate structure disposed on the surface of the well; a source electrode and a drain electrode, the source electrode being disposed in the well and located on one side of the gate structure, The drain is disposed in the well and is located on the other side of the gate structure, and the conductivity type of the source and drain is opposite to that of the well; the ion implantation region is disposed in the drain, and the conductivity type of the ion implantation region is the same as that of the well. The drain has the opposite conductivity type. This ion implantation region can reduce the doping concentration in the drain, increasing the probability of collision ionization of carriers and neutral atoms between the drain and the semiconductor base, thus reducing the occurrence of avalanche strikes between the drain and the semiconductor base. The required reverse voltage is passed through, thereby reducing the turn-on voltage of the ESD device.

Description

technical field [0001] The present application relates to the technical field of semiconductor integrated circuits, and in particular, relates to an ESD device, a manufacturing method of the ESD device, and an EEPROM. Background technique [0002] The entire life cycle of semiconductor integrated circuits from growth to packaging and testing will face various unpredictable electrostatic environments, which will easily introduce static electricity into semiconductor integrated circuits, which will cause electrostatic damage to semiconductor integrated circuits. Therefore, the design of semiconductor integrated circuits not only needs to meet functional requirements, but also has a certain electrostatic protection capability. Especially for EEPROM (Electrically Erasable Programmable Read-Only Memory), since the EEPROM contains many high-voltage devices, it needs to have a certain electrostatic protection capability. [0003] At present, ESD devices are usually designed in sem...

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Problems solved by technology

[0005] However, the turn-on voltage of the above-mentioned ESD device (referring to the absolute value of turn-on voltage here) is relatively high, so that it cannot meet the needs of semiconductor integrated circuits for electrostatic protection.

For example, HV 5V PMOS devices are usually used as ESD devices in existing EEPRPMs, and the turn-on voltage of HV 5V PMOS devices is usually -13V, while the design turn-on voltage of EEPRPM is -10V, which can no longer meet the needs of EEPRPM for electrostatic protection capabilities

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