Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device, comprising: a plurality of fins extending along a first direction on a substrate, extending along a second direction and crossing the gate of each fin, The source-drain region and the side wall of the gate, wherein the fin is composed of a buffer layer and a channel layer made of high-mobility material, and the buffer layer surrounds the side surface and the bottom surface of the channel layer. According to the semiconductor device and its manufacturing method of the present invention, by removing the dummy gate stack while increasing the etching depth and lateral width, a high carrier mobility can be locally aligned on the desired fin structure channel, thereby effectively improving the carrier mobility in the channel region of the fin, thereby effectively improving device performance and reliability.

Description

technical field [0001] The invention relates to a semiconductor device and a manufacturing method thereof, in particular to a three-dimensional multi-gate FinFET with high carrier mobility and a manufacturing method thereof. Background technique [0002] In the current sub-20nm technology, the three-dimensional multi-gate device (FinFET or Tri-gate) is the main device structure, which enhances the gate control capability and suppresses leakage and short channel effects. [0003] For example, compared with traditional single-gate bulk Si or SOI MOSFETs, MOSFETs with double-gate SOI structures can suppress short-channel effects (SCE) and drain-induced barrier lowering (DIBL) effects, have lower junction capacitance, and can To achieve light channel doping, the threshold voltage can be adjusted by setting the work function of the metal gate, which can obtain about 2 times the driving current and reduce the requirements for the effective gate oxide thickness (EOT). Compared wit...

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Problems solved by technology

Compared with the aforementioned method, although this method reduces the distribution of SiGe and Ge materials on the entire wafer, that is, the growth of some local spaces to a certain extent, as long as the fin structure on the top of the STI is exposed, the Ge epitaxial layer will grow. For other device regions on the wafer that need to further improve the electron mobility, it is difficult to adopt a CMOS compatible process to manufacture in one step, that is, an additional mask photolithography / etching process is often required, which increases the complexity of the device and easily causes device lines. Distortion, and even device failure

In addition, since the bottom of the fin structure is monocrystalline silicon (bulk Si or SOI top monocrystalline silicon) during epitaxial growth, and the STI on both sides of the epitaxial layer is amorphous oxide, it is easy to produce localized silicon during the epitaxial process. Lattice defects

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