Automatic analysis method capable of reconstructing start interval of periodic pipeline iteration in complier

Abstract

The invention discloses an automatic analysis method capable of reconstructing a start interval of periodic pipeline iteration in a complier. The method comprises steps of converting counting periodic codes into a SCoPS data structure, analyzing periodic pipeline iteration reading after writing RAW data dependence according to the counting periodic codes into a SCoPS data structure to acquire a counting periodic program RAW data dependence relationship analysis result RAW_DDA scanned by a RAW_DDA model, and conducting automatic analysis for the start interval of periodic pipeline iteration according to the counting periodic program RAW_DDA model to acquire an automatic analysis result of the start interval scanned by a periodic pipeline iteration non-fixed start interval model NF_II. By the use of the automatic analysis method, wait delayed time of the start interval of periodic pipeline iteration can be reduced and the method has universality.

Description

technical field [0001] The invention belongs to the field of reconfigurable computing, and in particular relates to an automatic analysis method for the startup interval between iterations of a loop pipeline in a reconfigurable compiler. Background technique [0002] At present, when studying the automatic mapping of multi-layer loop to parallel pipeline hardware structure, it mainly includes: (1) Represented by CGRA, the loop pipeline hardware structure mapping for coarse-grained reconfigurable hardware platform, through the function-level program feature analysis to achieve loop to The mapping of fixed pipeline hardware template structure can simplify the complexity of loop mapping, but it limits the versatility of loop programs to reconfigurable platforms; (2) VivadoHLS (HighLevelSynthesis, a high-level synthesis tool) proposed by Xilinx represents a detailed Granular reconfigurable compiler tool, through the analysis of cyclic program characteristics, completes the instr...

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Problems solved by technology

[0003] At present, the IMS (RausIterativeModuloScheduling) scheduling algorithm is used in the GarpCC compiler to realize the control mapping of the loop pipeline, but only the pipeline control is performed on the innermost loop; the pipeline vectorization method is used in the XPP, but it cannot handle the RAW data dependencies between the loop bodies. The interval between pipeline start-ups between non-innermost loop iterations; HLS tools such as VivadoHLS, ROCCC, and ImpulseC all use statement guidance to control the pipeline start-up interval between iterations when implementing multi-layer loop to pipeline parallel FPGA hardware structure mapping. Manually insert guidance statements similar to #pragmaII=xx in the source program C code loop to control the generation of start-up intervals between iterations after the loop is mapped into a pipeline parallel hardware structure

This method can only generate a fixed value of the startup interval between iterations for each layer of loops. At the same time, when using a reconfigurable compiler for reconfigurable computing application deployment, it is necessary to iterate the comprehensive simulation process repeatedly to determine the final appropriate value of the pipeline startup interval between iterations. , and no automatic analysis and related optimization methods are proposed, which greatly restricts the deployment efficiency of reconfigurable computing applications, and will also affect the promotion of fine-grained reconfigurable compilers in the industry

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