Single event transient (SET)-resistant reinforced register suitable for SRAM type FPGA for aerospace

Abstract

A single event transient-resistant reinforced register suitable for an SRAM type FPGA for aerospace is disclosed. A register unit performs processing on a SET pulse by a novel delay unit to make the register have high SET capability. The reinforced register consists of four parts of an internal data and clock generation circuit, a master latch, a slave latch and an output buffer. The internal data and clock generation circuit uses an NAND gate and an NOR gate to form a delay chain for processing the SET pulse; and the master latch and the slave latch use a latch unit based on a DICE (Dual Interlocked storage CEll) structure. The reinforced register, by using inherent characteristics of a DICE unit, only uses one delay chain to shield the SET pulses in a clock terminal CLK and a data terminal D at the same time. Compared with a conventional SET reinforced register, the reinforced register provided by the present invention has fewer delay units, so that the overall area of the reinforced register is smaller than that of the conventional reinforced register.

Description

Technical field [0001] The invention relates to an anti-single event transient reinforcement register suitable for aerospace SRAM type FPGA, and belongs to the technical field of anti-single event transient reinforcement register circuits. Background technique [0002] SRAM FPGAs for aerospace applications are particularly suitable for the high reliability, multi-variety, and low-volume characteristics of aerospace devices for aerospace engineering, and are widely used in aerospace engineering. With the advancement of processing technology, the density and performance of integrated circuits continue to increase, and the register unit in FPGA is facing more serious reliability problems in space applications: single event upset (SEU) and single event transient in the harsh environment of space (SET) and other single event effects. In order to eliminate, suppress or reduce the impact of single event effects on system functions, single event reinforcement technology has become a res...

AI Technical Summary

Problems solved by technology

[0003] The technical problem solved by the present invention is: to overcome the deficiencies of the prior art, to provide an anti-single-event transient hardening register suitable for SRAM type FPGA used in aerospace, and to make it have stronger anti-SET ability by performing SET hardening on the DICE unit , so as to alleviate the SET problem of SRAM FPGA in complex space environment

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