Phase-locked loop system

Abstract

Provided in the invention is a phase-locked loop system comprising a first-stage phase-locked loop and a second-stage phase-locked loop. The output terminal of the first-stage phase-locked loop is connected with the input terminal of the second-stage phase-locked loop; and the input terminal of the first-stage phase-locked loop is connected with a clock. The second-stage phase-locked loop contains phase-locked loops with the number corresponding to that of components in an application system; the phase-locked loops include feedback loops; input terminals of the phase-locked loops are adjacent to the output terminal of the first-stage phase-locked loop; and output terminals of the phase-locked loops approach input terminals of the corresponding components. According to the embodiment of the invention, a synchronous rate of clock signals received by all components of the application system and thus accuracy of data and command transmission between electronic devices is improved.

Description

technical field [0001] The invention relates to the field of electronic technology, in particular to a phase-locked loop system. Background technique [0002] PLL (phase locked loop, phase locked loop) is a frequency and phase synchronization technology realized by the principle of feedback control, which can be widely used in various electronic devices, so that the clock output by the circuit of the electronic device is synchronized with the external reference clock , when the frequency or phase of the reference clock changes, the PLL system will detect this change and adjust the output frequency through its internal feedback system until the two are resynchronized. [0003] In the process of transmitting the clock signal to the application system in the electronic device, the phase-locked loop is prone to jitter. The jitter may include: jitter1 brought by the phase-locked loop and the clock transmission path between the phase-locked loop and the above-mentioned application...

AI Technical Summary

Problems solved by technology

[0005] Because the clock signal is transmitted from the above-mentioned phase-locked loop 101, in the transmission path transmitted to the above-mentioned controller 102, command transmission interface 103 and data transmission interface 104, it will be affected by jitter2, therefore, the phase-locked loop 101 sends to the above-mentioned controller 102. The clock signals transmitted by the command transmission interface 103 and the data transmission interface 104 may be out of sync, which in turn makes the accuracy of data and commands transmitted between the SOC and the DRAM chip low

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