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Method for reducing intraframe coding time delay in HEVC encoder

An intra-frame coding and encoder technology is applied in the field of reducing the intra-frame coding delay in HEVC encoders to achieve the effects of reducing computational load, improving efficiency, and reducing intra-frame coding delay.

Active Publication Date: 2015-11-25
芯原微电子(北京)有限公司 +2
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

When the image size is relatively small, the delay of processing a maximum coding unit has not yet become the bottleneck of real-time encoding, but for the encoding of large-size images, this delay has become the main bottleneck of real-time encoding

Method used

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  • Method for reducing intraframe coding time delay in HEVC encoder
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  • Method for reducing intraframe coding time delay in HEVC encoder

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Embodiment Construction

[0047] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

[0048] The present invention provides a method for reducing intra-frame encoding delay in an HEVC encoder, comprising the following steps:

[0049] S1. Make a mode decision on the largest coding unit to be encoded, and obtain segmentation results and prediction mode decision results of all sub-coding units;

[0050] S2. Send all sub-coding unit segmentation results and prediction mode decision results of the LCU to be encoded to the scheduler;

[0051] S3. The sch...

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Abstract

The invention discloses a method for reducing intraframe coding time delay in an HEVC encoder. The method includes the following steps: S1 making mode decision to a largest code unit to be coded to obtain the segmentation result of all of the sub-coding units and predicted mode decision results; S2 sending the results selected by the largest code unit to be coded to a scheduler; S3 generating a data dependence graph of the basic unit of the current largest code unit by the scheduler through a method of reverse triggering of labels; S4 driving an intraframe coding unit to perform operation based on the data dependence graph; and S5 preparing the data needed by a next intraframe coding unit by the scheduler based on the operation result and triggering the next intraframe coding unit to operate. The method reduces the time delay of a largest code module in an intraframe coding mode, the streamline processing can be carried out, and the problem that how to determine the dependency of the code units in high efficient video coding is solved by the method of reverse triggering of labels.

Description

technical field [0001] The present invention relates to the technical field of video communication, in particular to a method for reducing intra-frame coding delay in an HEVC coder. Background technique [0002] In recent years, the global information industry has developed rapidly, and multimedia processing technology has gradually integrated with network communication technology, which has touched all aspects of national economy and social life. Consumer electronics, communications, film and television, broadcasting, and computer technology are increasingly closely integrated, making The Internet-based multimedia industry has become one of the fastest growing and largest industries. As an important part of multimedia information, video information is the most effective and important form of information acquisition, which accounts for about 70% of the information received in people's daily life. With the popularization and promotion of digital TV and network video, people ...

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Application Information

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IPC IPC(8): H04N19/11H04N19/176H04N19/186H04N19/127
Inventor 付桂鹏
Owner 芯原微电子(北京)有限公司
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