High-gain class AB operational amplifier circuit

Abstract

A class AB operational amplifier is widely applied to integrated circuits due to rail-to-rail output and high load current driving capability. In a conventional structure, a load tube of a differential input stage works in a critical saturation area, leading to low intrinsic gains of the devices and limiting the open-loop gain of the operational amplifier. A level translation circuit is added, so that the devices are separated from the critical saturation area, and the open-loop gain of the operational amplifier is increased greatly. A circuit in the invention consists of a bias circuit, a differential input stage, a level translation stage and an output stage.

Description

technical field [0001] The invention belongs to the field of integrated circuit design and is used for circuits requiring high-gain Class A and B operational amplifiers. Background technique [0002] In integrated circuit design, due to the rail-to-rail output and large load current driving capability of Class A and B operational amplifiers, it is widely used in integrated circuits. In the traditional structure, because the load MOS transistor of the differential input stage works in the critical saturation region, resulting in low intrinsic gain of these devices, which in turn limits the open-loop gain of the op amp; [0003] attached figure 1 It is a traditional class A and B operational amplifier circuit, which is widely used in the output stage of integrated circuit design; the specific circuit is composed of a bias circuit, a differential input stage, and an output stage; the bias circuit (a) consists of 2 NMOS tubes, 2 It consists of a PMOS transistor and two bias cu...

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Problems solved by technology

[0007] attached figure 2 It is the change curve of intrinsic gain with VDS voltage when the overdrive voltage of 3.3V NMOS device is 0.2V. It can be seen that the output resistance increases with the increase of VDS, and the intrinsic gain increases; for the above operational amplifier, in order to reduce the static power power consumption, the output stages MN0 and MP0 are weakly turned on, VGN≈VTH NMOS 、VGP≈VDD-VTH PMOS , For the threshold voltage of typical 5V process NMOS and PMOS is about 0.6V, then the VDS voltage of the load transistors M4, M6, M8, M10 is about 0.3V, and they are all in the critical saturation region at this time, and the intrinsic gain is only 34.7, resulting in The open-loop gain of the op amp is low

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