8421BCD code synchronization decimal addition/subtraction counter based on reversible logic

Abstract

The invention discloses an 8421BCD code synchronization decimal addition / subtraction counter based on reversible logic, and the counter comprises four reversible master-slave JK contactors based on a reversible logic structure, and five transition modules, wherein the four reversible master-slave JK contactors and the five transition modules are cascaded according to the mutual reference relationship among all input and output ends. Meanwhile, the output CP end and input CP end of each reversible master-slave JK contactor are sequentially cascaded, thereby obtaining the counter. The counter is lower in energy loss, and can achieve a function of addition / subtraction counting on the basis of further reducing system power consumption and circuit implementation cost remarkably. The master-slave JK contactors do not have flip phenomenon, are good in anti-interference performance, and are high in working speed. A logic circuit is simple, is ordered in layout, is easy to construct, and also has a function of self-start.

Description

technical field [0001] The invention relates to the design of low-power sequential logic circuits in the field of information technology, in particular to an 8421BCD code synchronous decimal addition / subtraction counter based on reversible logic. Background technique [0002] In the digital system, the counter can not only count the number of pulses, but also have multiple functions such as frequency division, timing, generation of beat pulses and pulse sequences, and digital operations. In particular, the decimal counter is the most widely used, and the most commonly used two basic functions are addition counting and subtraction counting. Therefore, the addition / subtraction circuit of the decimal counter is designed and the addition and subtraction counting are integrated in the same circuit to realize Reversible counting is necessary. [0003] Landaure has confirmed that the erasure of information bits in traditional irreversible logic circuits will lead to energy loss, a...

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Problems solved by technology

[0003] Landaure has confirmed that the erasure of information bits in traditional irreversible logic circuits will lead to energy loss, and the erasure of each bit of information corresponds to the heat generation of KT ln2 joules, where K is the Bowitzmann constant, and T is the heat generated when performing operations. absolute temperature

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