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A fence synchronization method and device

A fence synchronization and fence technology, applied in the field of communication, can solve the problem of chip processing performance degradation

Active Publication Date: 2018-06-05
HUAWEI TECH CO LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The present invention provides a barrier synchronization method and device, which solves the problem of the decline in processing performance of chips with multi-core or many-core processors caused by access bottlenecks when the number of threads increases

Method used

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  • A fence synchronization method and device
  • A fence synchronization method and device
  • A fence synchronization method and device

Examples

Experimental program
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Effect test

Embodiment 1

[0095] Embodiment 1 of the present invention provides a barrier synchronization method, which is applied to a chip with a multi-core or many-core processor, and at least two barrier synchronization devices are provided on the chip, such as figure 1 As shown, the method may include:

[0096] 101. The first processor core determines that a currently processed thread program is executed to a predetermined barrier synchronization point. Wherein, the first processor core is any one of all processor cores included in the chip.

[0097] 102. The first processor core determines a target barrier synchronization device according to a barrier identifier corresponding to a predetermined barrier synchronization point.

[0098] Wherein, the fence synchronization method of the embodiment of the present invention is applied to a chip with a multi-core or many-core processor, and at least two fence synchronization devices are arranged on the chip, when any processor core in all processor core...

Embodiment 2

[0104] Embodiment 2 of the present invention provides a barrier synchronization method, which is applied to a chip with a multi-core or many-core processor, and at least two barrier synchronization devices are arranged on the chip, such as figure 2 As shown, the method may include:

[0105] 201. The target barrier synchronization device receives a barrier synchronization message sent by the first processor core.

[0106] Wherein, the barrier synchronization message is sent by the first processor core when it is determined that the currently processed thread program executes to a predetermined barrier synchronization point, the first processor core is any one of all processor cores contained in the chip, and the barrier synchronization message contains the fence identifier corresponding to the fence synchronization point and the number of thread programs participating in the synchronization, and the target fence synchronization device is a fence synchronization device for proc...

Embodiment 3

[0113] Embodiment 3 of the present invention provides a barrier synchronization method, which is applied to a chip with a multi-core or many-core processor. At least two barrier synchronization devices are provided on the chip, and the at least two barrier synchronization devices are distributed in the network on chip. different locations, for example image 3 The shown embodiment of the present invention provides a schematic structural diagram of a chip provided with four barrier synchronization devices and has a multi-core or many-core processor. Such as Figure 4 As shown, the barrier synchronization method provided in the embodiment of the present invention may include:

[0114] 301. The first processor core determines that a currently processed thread program is executed to a predetermined fence synchronization point.

[0115] Wherein, the first processor core is any one of all processor cores included in the chip.

[0116] 302. The first processor core determines a ta...

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Abstract

The invention discloses a fence synchronization method and equipment, relates to the field of communication, and solves the problem that the processing performance of chips with multi-core or many-core processors decreases due to access bottlenecks when the number of threads increases. The specific solution is: the first processor core determines that the currently processed thread program executes to a predetermined barrier synchronization point; the first processor core is any one of all processor cores included in the chip; according to the predetermined barrier synchronization The barrier identification corresponding to the point determines the target barrier synchronization device; sends a barrier synchronization message to the target barrier synchronization device; the barrier synchronization message includes the barrier identification and the number of thread programs participating in the synchronization. The present invention is used in the process of fence synchronization.

Description

technical field [0001] The present invention relates to the communication field, in particular to a fence synchronization method and equipment. Background technique [0002] Traditional single-core processors usually increase the main frequency of the processor by using superscalar and pipeline processing technology to achieve the purpose of improving processor performance, but the increase of main frequency will lead to increased power consumption of the processor, and will lead to The heat dissipation of the processor is not good. Moreover, with the continuous development of semiconductor technology, the number of transistors that can be integrated on the chip is gradually increasing. In order to improve the performance of the processor and reduce the power consumption of the processor at the same time, and to make the processor have good heat dissipation, the architecture designer proposes Multi-core or many-core processors with thread-level coarse-grained parallelism. ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/52
Inventor 徐卫志
Owner HUAWEI TECH CO LTD
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