Flash chip and flash chip erasing method

Abstract

The invention relates to the technical field of memories and particularly relates to a flash chip and an erasing method thereof. The flash chip comprises a memory array, m word line driving sub-circuits and a bit line selecting circuit, wherein the memory array comprises m memory subarrays and a redundancy unit zone; the m memory subarrays are formed in one well region; the redundancy unit zone is formed between two adjacent memory subarrays; during erasing, a drain electrode of a memory unit in the redundancy unit zone is suspended in midair; the m word line driving sub-circuits are respectively connected to the m memory subarrays; each word line driving sub-circuit provides driving signal to the memory subarray connected to the corresponding word line driving sub-circuit; and the bit line selecting circuit provides a plurality of bit lines, is connected to drain electrodes of memory units of the memory subarrays in each row of the memory array and is used for selecting the memory units in the memory subarrays. Erasing performance of the flash chip provided by embodiments is improved and erasing time of the flash chip is shortened, thus increasing the erasing efficiency.

Description

technical field [0001] The invention relates to the technical field of memory, in particular to a FLASH chip and an erasing method using the FLASH chip. Background technique [0002] In the prior art, when flash memory (Flash Memory) is erased, a positive high voltage is applied to the well region where the memory cell is located in the pre-erased area and the source (S) of the pre-erased memory cell, and a negative high voltage is applied to the control gate (CG), and Floating drain (D); in this way, the applied positive and negative high voltages form a voltage difference between the floating gate (FG) and source of the memory cell, creating a tunnel effect that allows charges in the floating gate to flow to the source , and then change the threshold voltage of the memory cell to realize erasing of the pre-erased memory cell. At the same time, when erasing, the same positive high voltage is applied to the source of the memory cells in the non-erased area in the same well ...

AI Technical Summary

Problems solved by technology

However, in the prior art, the erasing repair operation performed to eliminate erasing interference prolongs the erasing time and increases the time overhead of the erasing operation, thereby reducing the erasing efficiency

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