Method for forming Y-shaped gate metal dielectric hole through auxiliary of photoresist

Abstract

The invention provides a method for forming a Y-shaped gate metal dielectric hole through auxiliary of photoresist. The method comprises the following steps that 1) coverage of photoresist on a Y-shaped gate metal strip is formed through the photoetching technology; 2) SiN dielectric is grown at low temperature; 3) dielectric holing is performed at the two end heads of the gate metal strip through the photoetching and dielectric etching technology; 4) a Y-shaped gate dielectric hole is formed by removing photoresist of a sacrificial layer; and 5) the grown SiN dielectric seals the dielectric holes of the two end heads of the gate metal strip. Advantages are that the gate metal dielectric hole formed by the method is larger and reduction of gate parasitic capacitance is more significant so that the method has positive significance in reducing device gate parasitic capacitance of submicron and deep submicron gate length second-generation and third-generation semiconductor field effect devices of millimeter wave applications.

Description

technical field [0001] The invention relates to a method for improving the high-frequency performance and noise performance of second-generation and third-generation semiconductor field-effect devices with submicron and deep submicron gate lengths, which relies on photoresist to assist in forming a Y-shaped gate metal dielectric cavity. It belongs to the field of semiconductor technology. Background technique [0002] For microwave and millimeter wave field effect transistors, one of the main means to improve their frequency characteristics is to reduce the gate length of the device to reduce the channel electron transit time; the development of small gate length GaAs and InP HMET / PHEMT devices at home and abroad has reached less than 100nm level. For such a small gate length, the greatly increased gate resistance has become an important factor restricting device performance; in order to solve the problem of large gate resistance of devices with small gate lengths, T-shaped...

AI Technical Summary

Problems solved by technology

The traditional gate dielectric void formation method utilizes the dielectric deposition gas to have different mass transport rates at different positions under the gate metal, resulting in different growth rates to form plugged voids. As shown in Figure 1, the dielectric voids obtained by this method are usually The size is small, so the reduction of gate parasitic capacitance is limited

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