Vertical-structure LED chip manufacturing method

Abstract

In order to raise the processing yield of vertical-structure LED chips, the present invention provides a novel method for manufacturing the-vertical structure LED chips, which can notably reduce electric leakage of the chips and raise the chip production yield. A P electrode of the chip is formed on the surface of the chip, an N electrode of the chip is bonded with a silicon / copper / tungsten copper alloy substrate, and the P electrode is welded with a support during packaging of the chip. Combination of the ICP etching technique and the hot acid corrosion technology is adopted to form chip isolation channels. A laser spot is adjusted during laser stripping so as to be matched in size with the chip after the isolating channels are formed. An epitaxial wafer is bonded on the silicon / copper / tungsten copper alloy substrate through a high-temperature bonding technique, the ultrasonic technology is then used, and by using internal stress produced in the bonding process and the ultrasonic vibration technology, separation of gallium nitride and the substrate is further raised.

Description

Technical field: [0001] The invention relates to a method for preparing a vertical structure LED chip, belonging to the field of LED chip preparation. Background technique: [0002] LED has become the third-generation lighting source after incandescent lamps and fluorescent lamps. Compared with traditional lighting sources, LED semiconductor lighting sources have the following advantages: high luminous efficiency, small size, long life, energy saving, and environmental protection. At present, one of the main reasons why LEDs have not entered general lighting on a large scale is that LED luminous efficiency and heat dissipation conditions need to be further improved, and the second is to reduce the production cost of LEDs. Since the vertical structure LED satisfies good heat dissipation conditions, it can be driven with a larger current, thereby improving the LED luminous efficiency. Therefore, the vertical structure LED will accelerate the process of LED application in the...

AI Technical Summary

Problems solved by technology

One of the biggest problems encountered at present is that more defects and stress are generated during the growth process of GaN-based epitaxial wafers. During the wafer bonding process, the temperature needs to be raised. When the temperature is lowered, the number of defects in GaN will further increase and the number of internal defects will increase. The stress is further increased, so the wafer bonding process will damage the GaN epitaxial layer, resulting in large chip leakage; the second is to use the laser lift-off technology to scan the wafer through the focused laser spot, and the distance between the spot and the spot during scanning is The overlapping will lead to energy unevenness, and the uniformity of the process is poor, resulting in uneven peeling of the GaN / sapphire interface, which leads to low laser peeling yield and large leakage of processed chips; the third is the process of manufacturing N electrodes after laser peeling In the process, the N-type GaN layer needs to be etched by ICP. Since the N-type GaN surface is rough and uneven after laser lift-off, it is difficult to control the etching depth during the ICP etching process, which will cause high voltage and leakage of the vertical structure chip. bigger

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