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Method and architecture of wireless multi-core array hotspot elimination based on butterfly network coding

A butterfly network, hotspot technology, applied in the field of communication, can solve the problem of multiple hotspots, limited flexibility and scalability, etc.

Active Publication Date: 2018-01-02
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, the wired connections in the prior art limit the flexibility and scalability of network coding applications in wired multi-core arrays; and, in these designs, only one butterfly network code is used in the multi-core array architecture, which is far from being able to solve complex business on-chip Multiple hotspots caused by load

Method used

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  • Method and architecture of wireless multi-core array hotspot elimination based on butterfly network coding
  • Method and architecture of wireless multi-core array hotspot elimination based on butterfly network coding
  • Method and architecture of wireless multi-core array hotspot elimination based on butterfly network coding

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Embodiment 1

[0125] The implementation process of the task graph for 48 subtasks in the multi-core array with 9×9Mesh topology is as follows:

[0126] (1) Determine the location of the hot spot in the network;

[0127] First, determine the location of the hotspot node in the wireless multi-core array;

[0128] In the Mesh multi-core array, the simplest butterfly network code occupies a 3×3 rectangular area, and the upper limit of the number of butterfly network codes in 9×9 Mesh is:

[0129]

[0130] That is, the number of nodes that can relieve congestion through butterfly network coding does not exceed 9.

[0131] Press the 48 subtasks as Figure 7 The order shown maps to the corresponding multicore array node. The total communication traffic of each node on the multi-core array can be obtained from the mapping relationship like Figure 8 , where the numbers in the row indicate the abscissa, and the numbers in the column indicate the ordinate. ]

[0132] In this example, the red...

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Abstract

The present invention relates to the field of communication, in particular to the field of wireless multi-core parallel processing, and specifically refers to a wireless multi-core array hotspot elimination method and architecture based on butterfly network coding; a wireless multi-core array architecture using distributed butterfly network coding is proposed, through multiple The disjoint butterfly network coding improves the network throughput of the wireless multi-core array, reduces the number of hotspots in the multi-core array, and provides an efficient and parallel multi-core collaborative processing platform for complex systems. At the same time, the present invention proposes a minimization hotspot algorithm to optimize the design of the wireless multi-core array architecture, aiming at maximizing the number of codes in the butterfly network to obtain the maximum coding gain. Through verification, the architecture proposed by the present invention can achieve at least 4% increase in throughput with less overhead, and eliminate at least 43% of hot spots in the network.

Description

technical field [0001] The invention relates to the communication field, in particular to a method and framework for eliminating hotspots in a wireless multi-core array based on butterfly network coding. Background technique [0002] The network on chip (multi-core array, network on chip) is an efficient interconnection architecture proposed to solve the network transmission bottleneck of the system on chip (SoC, system on chip) based on the bus structure. With the rapid development of parallel processing, applications carried on multi-core arrays include more and more communication requirements. With the increase of SoC scale, the speed of on-chip metal wiring cannot keep up with the growth of system scale, and on-chip wired connection becomes the bottleneck restricting the performance of multi-core array network. The wireless multi-core array, with its advantages of high bandwidth, reconfigurability and broadcasting, provides a feasible design solution for high-performanc...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L12/801G06F15/78
Inventor 陈亦欧凌翔胡剑浩谭芳
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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