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Error recovery method based on lockstep architecture

An error recovery and processor technology, applied in the computer field, can solve the problem of low real-time fault detection, achieve good real-time performance, improve fault tolerance, and achieve simple effects

Active Publication Date: 2015-06-10
AVIC NO 631 RES INST
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  • Application Information

AI Technical Summary

Problems solved by technology

Traditional computer fault detection is mainly realized by watchdog, closed-loop detection and other methods, and the fault detection rate is difficult to reach more than 98%. Comparing calculation results and monitoring can achieve a high fault detection rate, but the real-time performance of fault detection is not high

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  • Error recovery method based on lockstep architecture

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Embodiment Construction

[0023] The present invention uses the bus lock-step and monitoring module (abbreviation: Lock-Step module) to carry out synchronous "bit-by-bit" comparison of two processor bus cycle operation transactions (reading, writing), and detects the working conditions of the two computers in real time , and save the processor state. After the processor comparison finds inconsistencies, restore the processor state to the last saved state, which can restore various errors caused by transient faults in the processor memory and transient errors generated on the memory bus. , and errors generated by the internal operation of the processor. Thus, a highly reliable processor is realized.

[0024] The Lock-Step computer for bus monitoring consists of figure 1 As shown, the processor part is two synchronously running processors, which can be compared synchronously to detect the occurrence of errors. Every fixed time slice after processor synchronization, the processor state is written into t...

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Abstract

The invention relates to an error recovery method based on a lockstep architecture. The method comprises steps as follows: 1) Lock-Step module running state and switching: after a Lock-Step module is powered on, state is saved on the basis of the time stream, a hardware signal is sent through a hardware timer after a period, and software saves the state of a processor after reading the state; 2) the state of hardware is switched, saving recovery of the hardware is divided into two states, namely, a running state and a saving state, if the processor performs the write operation in the running state, the operation of writing of address data of an SM is finished by the SM in the time slice of the running state, and data consistency is guaranteed. According to the error recovery method based on the lockstep architecture, transient errors of running of a computer running can be discovered under the computer architecture, the errors can be recovered by a recovery mechanism, the error-tolerant capability of the computer can be improved, and the reliability of the computer is high.

Description

technical field [0001] The invention belongs to computer technology, and relates to an error recovery of a bus monitoring Lock-Step computer to realize high reliability, including a hardware mechanism and a software mechanism of error recovery. Background technique [0002] The high fault detection rate of computer is very important for its application in safety-critical fields. Traditional computer fault detection is mainly realized by watchdog, closed-loop detection and other methods. It is difficult to achieve a fault detection rate of more than 98%. Comparing calculation results and monitoring can achieve a high fault detection rate, but the real-time performance of fault detection is not high. . Lock-Step computer is another method to realize high-integrity computing. Lock-Step can detect faults with high probability and detect faults in real time. After a fault is detected, a recovery mechanism can be used to recover from the error, thereby realizing a computer with ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/07G06F11/30
Inventor 周啸李鹏韩强邓豹沈华
Owner AVIC NO 631 RES INST
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