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Branch prediction preloading

A technology of branch prediction and preloading, which is applied in the direction of instrumentation, computing, and concurrent instruction execution, and can solve problems such as pipeline stagnation

Active Publication Date: 2015-02-04
IBM CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

A conditional branch instruction in the instruction stream can cause a pipeline stall if the processor waits until the conditional branch instruction is resolved in the execute stage of the pipeline before fetching the next instruction in the instruction fetch stage of the pipeline

Method used

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Examples

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Embodiment Construction

[0018] Exemplary embodiments enable branch prediction preloading. As code executes repeatedly and branches are encountered abruptly, branch prediction is typically learned over time, installing only those branches known through the decoding process in a branch target buffer (BTB). Once the BTB is filled with information indicating the branch address, target address and direction, such as taken and not taken items, the prediction accuracy increases because the BTB is updated after the branch prediction is resolved. Exemplary embodiments provide branch predictive preloading using branch predictive preload instructions so that branch instruction addresses and target addresses can be inserted into the BTB before the associated branch is taken. When writing software or compiling software, the code can be analyzed to look for branch instructions. Branch prediction preload instructions can be appended to code preceding branches so that subsequent branches can be accurately predicted...

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Abstract

Embodiments relate to branch prediction preloading. A method for branch prediction preloading includes fetching a plurality of instructions in an instruction stream, and decoding a branch prediction preload instruction in the instruction stream. The method also includes determining, by a processing circuit, an address of a predicted branch instruction based on the branch prediction preload instruction, and determining, by the processing circuit, a predicted target address of the predicted branch instruction based on the branch prediction preload instruction. The method further includes identifying a mask field in the branch prediction preload instruction, and determining, by the processing circuit, a branch instruction length of the predicted branch instruction based on the mask field. Based on executing the branch prediction preload instruction, a branch target buffer is preloaded with the address of the predicted branch instruction, the branch instruction length, and the predicted target address associated with the predicted branch instruction.

Description

technical field [0001] The present invention relates generally to computer processing systems, and more particularly to branch prediction preloading. Background technique [0002] Instruction pipelines in computer processors improve instruction execution throughput by processing instructions through a large number of pipeline stages, where multiple stages can act in parallel on different instructions in the instruction stream. A conditional branch instruction in an instruction stream may cause a pipeline stall if the processor waits until the conditional branch instruction is resolved in the execute stage of the pipeline before fetching the next instruction in the instruction fetch stage of the pipeline. A branch predictor can try to speculate whether to take a conditional branch. Branch predictors may also include branch target prediction, which attempts to speculate on the target of a taken conditional or unconditional branch before computing it by decoding and executing ...

Claims

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Application Information

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IPC IPC(8): G06F9/38
CPCG06F9/3806G06F9/3844G06F9/30058G06F9/3005
Inventor B.R.普拉斯基A.瓦西利夫斯基J.J.博南诺J.休M.米特兰T.斯莱格尔
Owner IBM CORP
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