MOS transistor with stacked nanometer lines and manufacturing method of MOS transistor

Abstract

The invention discloses an MOS transistor with stacked nanometer lines and a manufacturing method of the MOS transistor. The MOS transistor comprises toruliform nanometer line stacks, a plurality of grid stacks, a plurality of source and drain regions and a plurality of channel regions, wherein each nanometer line stack is formed by stacking the nanometer lines in the longitudinal direction and extends on a substrate in the first direction; the grid stacks extend in the second direction and cross over the nanometer stacks; the source and drain regions are located on the two sides of each grid stack in the second direction; the channel regions are formed by the nanometer line stacks between the source and drain regions. According to the MOS transistor with the stacked nanometer lines and the manufacturing method of the MOS transistor, the toruliform nanometer line stacks with good quality are formed by means of etching carried out many times and sideward etching and filling of grooves, effective widths of conducting channels are increased at low cost, the total area of effective conductive sections is increased and drive currents are increased.

Description

technical field [0001] The invention relates to a semiconductor device and a manufacturing method thereof, in particular to a novel beaded stacked nanowire MOS transistor and a manufacturing method thereof. Background technique [0002] In the current sub-20nm technology, the three-dimensional multi-gate device (FinFET or Tri-gate) is the main device structure, which enhances the gate control ability and suppresses leakage and short channel effects. [0003] For example, compared with traditional single-gate bulk Si or SOI MOSFETs, MOSFETs with double-gate SOI structures can suppress short-channel effects (SCE) and drain-induced barrier lowering (DIBL) effects, have lower junction capacitance, and can To achieve light channel doping, the threshold voltage can be adjusted by setting the work function of the metal gate, which can obtain about 2 times the driving current and reduce the requirements for the effective gate oxide thickness (EOT). Compared with the double-gate dev...

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Problems solved by technology

This method is severely limited by the quality of the epitaxial thin layer, which greatly increases the process cost

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