Medium-resolution-ratio and high-speed configurable asynchronous successive approximation type analog-digital converter

Abstract

The invention provides a medium-resolution-ratio and high-speed configurable asynchronous successive approximation type analog-digital converter. The medium-resolution-ratio and high-speed configurable asynchronous successive approximation type analog-digital converter comprises a sampling network, a comparator, a successive approximation control unit, an output latch and an asynchronous control unit. The sampling network is composed of a bootstrap switch and differential capacitor arrays, wherein the differential capacitor arrays comprise a first capacitor array and a second capacitor array, and the first capacitor array and the second capacitor array are composed of capacitor sets which are of a whole binary system structure. The comparator is used for comparing the voltage output by the first capacitor array and the voltage output by the second capacitor array. The successive approximation control unit is used for finishing the successive approximation process of the voltage output by the first capacitor array and the voltage output by the second capacitor array. The output latch is used for latching and outputting digital signals obtained after converting is finished. The asynchronous control unit is used for producing clock signals of the comparator. The converting speed of the analog-digital converter can be improved.

Description

technical field [0001] The invention relates to the field of analog-to-digital converters, in particular to a medium-resolution high-speed configurable asynchronous successive approximation analog-to-digital converter. Background technique [0002] Successive approximation analog-to-digital converter (SAR ADC) is a type used in medium precision and medium sampling rate, and is widely used in various medical, portable and communication systems because of its simple structure, small area, and high power utilization . Since the successive approximation analog-to-digital converter does not require linear gain blocks such as operational amplifiers, the SAR ADC can better adapt to the technological evolution trend of reduced feature size and lower power supply voltage. With the advancement of technology, the conversion rate that SAR ADC can achieve has also increased to hundreds of megabytes, which can be compared with pipeline analog-to-digital converters, and has higher power c...

AI Technical Summary

Problems solved by technology

[0003] For the successive approximation analog-to-digital converter of the traditional structure, a higher-speed comparison control clock signal (generally several times the sampling rate) is required internally, which will increase the design difficulty and power consumption of the analog-to-digital conversion, and limit the analog-to-digital converter conversion speed

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