A scr device with high sustain voltage embedded gdpmos

Abstract

An SCR device with high sustain voltage embedded GDPMOS for ESD protection circuits of high voltage on-chip ICs. Mainly composed of P substrate, N well, P well, first N+ implantation region, first P+ implantation region, second P+ implantation region, second N+ implantation region, third N+ implantation region, third P+ implantation region, metal anode , metal cathode, polysilicon gate, thin gate oxide layer and several field oxygen isolation regions. Under the action of high-voltage ESD pulses, the SCR device with high sustain voltage embedded GDPMOS, on the one hand, forms a parasitic SCR current discharge by the first P+ injection region, N well, second N+ injection region, P well, and third N+ injection region. path, improve the failure current of the device, and enhance the ESD robustness of the device; on the other hand, the PMOS transistor formed by the first P+ implantation region, the polysilicon gate, the thin gate oxide layer and the second P+ implantation region is connected to a high potential through the gate A GDPMOS tube is formed to suppress the strong hysteresis of the SCR device, increase the sustain voltage of the device, and enhance the anti-latch-up ability of the device.

Description

technical field [0001] The invention belongs to the field of electrostatic discharge protection of integrated circuits, relates to an ESD protection device, in particular to an ESD protection device with an SCR structure with high sustain voltage, which can be used to improve the reliability of IC high-voltage ESD protection on a chip. Background technique [0002] With the rapid development of integration technology, electronic products are increasingly miniaturized. While improving the performance and integration of integrated structures, the internal structure of integrated circuits is more likely to be damaged when ESD strikes, and the reliability problems caused by ESD are becoming more and more serious. draw people's attention. According to the investigation of various factors that cause the failure of integrated circuit products, it is found that the economic losses caused by ESD in the semiconductor industry are as high as billions of dollars every year. Therefore, ...

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Problems solved by technology

[0004] Aiming at problems such as insufficient anti-latch-up ability generally existing in the ESD protection device of existing SCR structure, the example of the present invention designs a kind of ESD protection device with the new SCR structure of high holding voltage, has not only made full use of the strong SCR device The characteristics of robustness, and the increase of the layout level of the thin gate oxide layer covered by P+, polysilicon gate and polysilicon gate in the device, make the device form an embedded GDPMOS structure, under the action of ESD pulse, through a comprehensive trade-off And reasonable control of the layout parameters of the channel length of the PMOS transistor can obtain low trigger, high sustain voltage, and strong robustness ESD protection devices suitable for high-voltage IC circuits

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