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Memory

A memory and storage unit technology, applied in the field of memory, can solve problems such as low wiring efficiency, and achieve the effects of improving wiring efficiency, reducing wiring congestion, and reducing distribution

Inactive Publication Date: 2014-12-17
NVIDIA CORP
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  • Summary
  • Abstract
  • Description
  • Claims
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Problems solved by technology

In order to solve the congestion problem, it is necessary to use the routing resources of the higher metal layer of the memory, and the routing efficiency is low

Method used

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Embodiment Construction

[0034] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order not to obscure the invention.

[0035] figure 1 A dual port memory 100 is shown. Such as figure 1 As shown, the dual-port memory 100 may include an address enable flip-flop 110 , a control circuit 120 , a decoding module, a memory cell sub-array 150 , and an input-output circuit 160 and other components. The decoding module includes a pre-decoding module 130 and a first final decoding module 140 . The memory cell subarray 150 is divided into two groups. The address enable flip-flop 110, the control circuit 120, the pre-decoding module 130, and the first final decoding module 140 are located between the two grou...

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Abstract

The invention provides a memory including two groups of memory cell subarrays and decoding modules arranged side by side between the two groups of memory cell subarrays. Each decoding module comprises at least one pre-decoding module, at least one first final decoding module and at least one second final decoding module. The number of the first final decoding modules is the same as the number of the pre-decoding modules. Each first final decoding module is connected with one corresponding pre-decoding module via a first pre-decoding address signal line. Each second final decoding module is connected with one corresponding pre-decoding module via a second pre-decoding address signal line. The first final decoding module and the second final decoding module connected to the same pre-decoding module are respectively located on two sides of the same pre-decoding module. The memory effectively reduces the distribution of word lines in the decoding modules, so as to reduce wiring congestion in the memory and improve the wiring efficiency.

Description

technical field [0001] The present invention relates generally to the field of data storage, and, more particularly, to a memory. Background technique [0002] For today's chips, memory consumes a significant amount of die area and has been the bottleneck that limits chips to running at lower operating voltages and higher speeds. In addition, in place-and-route design, memory has always occupied a large amount of metal routing resources and caused serious routing congestion problems of higher metal layers, such as the fifth metal layer in the 40nm process. [0003] For memory, it is the word line rather than the clock that dictates the design. The parasitic resistance-capacitance (RC) delay of the word line greatly affects the required target frequency and minimum supply voltage. [0004] One-sided structure is one of the most commonly used structures in memory design. In a single-sided structure, the memory includes a set of memory cell arrays and decoding modules. The ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C8/16G11C8/10
Inventor 黄永昌
Owner NVIDIA CORP
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