Method for forming seed crystal layers in silicon through hole technology

Abstract

The invention provides a method for forming seed crystal layers in a silicon through hole technology. The method comprises the steps that a first-time seed crystal layer deposition process is conducted in a silicon through hole, and first seed crystal layers are formed in the silicon through hole and on the outer surface of the top of the silicon through hole; a backflow process is conducted on the first seed crystal layers, and the first seed crystal layers with the smooth surfaces are formed; a second-time seed crystal layer deposition process is conducted in the silicon through hole, and second seed crystal layers are formed on the surfaces of the first seed crystal layers. Due to the fact that the prepared seed crystal layers are provided with the smooth surfaces, advantageous conditions are provided for the subsequent copper electroplating, the detect that holes are generated inside the padded copper is effectively overcome, the technological quality of copper electroplating is improved, and the reliability of the silicon through hole is ensured.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for forming a seed layer in a through-silicon via process. Background technique [0002] In the process development of VLSI, with the further development of Moore's Law, some process parameters have approached the physical limit, such as the resolution in the photolithography process, the dielectric thickness in the gate process in the device, and the barrier in the interconnection. layer thickness etc. The TSV process can reduce the use area of ​​silicon wafers, improve silicon utilization and shorten the interconnection length, so that Moore's Law can be further extended and expanded. Through Silicon Via (TSV) has become a research hotspot. TSV technology includes 2.5D, 3D, etc., among which 2.5D is a silicon (Si) interposer (interposer), which integrates chips with different functions such as CPU (central processing unit), Memory (memory), etc. in the TSV. On...

AI Technical Summary

Problems solved by technology

In the actual process production, due to the limitation of the Bosch etching process itself, the sidewall of the through-silicon via is often not smooth, which will make it difficult to form a good sidewall coverage in the subsequent film deposition process, and further cause the subsequent formation of TSVs. The surface of the seed layer is uneven or discontinuous, which seriously affects the effect of copper filling, and void defects appear inside the filled copper

Images