Embedded chip interconnecting and packaging method based on aluminum anodizing technology and structure

Abstract

The present invention relates to an embedded chip interconnecting and packaging method based on an aluminum anodizing technology and a structure. The method comprises the steps of selecting a low-cost aluminum sheet as a chip embedded substrate, and making a double-face and porous alumina film by the aluminum anodizing technology; obtaining a cavity structure of an embedded chip by utilizing the aluminum chamber protection characteristic of a rectangular ring and the selective corrosion characteristic of the porous alumina film, and finishing the chip coplanar embedment; finishing the interconnection of the embedded chip by the technologies, such as a right side dielectric layer filling photoetching technology, a film metal layer wiring technology, etc. According to the present invention, the positioning precision is high, the size of an embedded cavity matches the chip very well, and the low-cost and coplanar embedment problem of the chips of different sizes is solved effectively. By designing the back side aluminum flux columns, the heat radiation problem of the chip can be solved very well. A dielectric layer having a low dielectric constant can be used as a surface protection film, an interlayer insulation film or a porous alumina depth groove filler of the chip, especially can solve the problems of flattening the surface of an aluminum substrate, improving the bending or warping of the substrate, and satisfies a film technology.

Description

technical field [0001] The invention belongs to the technical field of semiconductor packaging, in particular to an embedded chip interconnection method based on aluminum anodic oxidation technology. Background technique [0002] Embedded chip interconnection technology is to embed the chip in the substrate or dielectric layer, and then uniformly carry out metal wiring, so as to naturally connect the soldering area of ​​the chip with the wiring metal. The interconnection between the chip bonding area and the substrate bonding area is a part of the metal wiring, and there is no trace of "welding" in the interconnection. Embedded chip interconnection can further improve the density of electronic assembly and the reliability of electronic products. It is an effective form to further realize three-dimensional packaging. The manufacturing process does not require solder, and a large number of defects directly or indirectly related to solder and reflow will disappear, thereby imp...

AI Technical Summary

Problems solved by technology

On the one hand, dry etching or wet etching processes are often used when processing embedded chip cavities. Dry etching has high positioning accuracy, but high processing costs have become a major obstacle for mass production, processing, and integrated applications. obstacle

However, wet etching of silicon substrates is easy to form an inverted trapezoidal structure with an inclination angle of 50°-60°. The control accuracy of the etching process is poor, resulting in low chip positioning accuracy; During the connection, after depositing the metal layer and the dielectric layer, there will be large bending and warping problems, which will affect the reliability of the product

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