LDPC encoding method based on bit stuffing

Abstract

An LDPC encoding method based on bit stuffing is characterized by comprising the steps that (1) synchronous head and information bit extraction is performed on received AOS standard frame data, and n bit parallel information bit data flow capable of performing parallel encoding is obtained through information bit sorting and bit stuffing; (2) extension is performed to generate a matrix; (3) LDPC parallel encoding is performed to generate a check bit; (4) sorting is performed to form AOS standard frame format data flow for output. The LDPC encoding method based on bit stuffing has the advantages of being low in hardware overhead, high in processing speed and applicability, easy to implement in an engineering mode, stable and reliable; besides, the design method has obvious advantages in application in the aerospace field.

Description

technical field [0001] The invention belongs to the technical field of satellite remote sensing, in particular to an LDPC encoding method based on bit stuffing. Background technique [0002] With the rapid development of satellite remote sensing technology, LDPC encoders must complete the processing and transmission of massive data of various payloads in real time. For this reason, a new generation of space-borne high-speed LDPC encoders has been developed. The new generation of space-borne high-speed LDPC encoders requires The data rate that can be completed is 5Gbps, and the traditional serial processing LDPC coder can no longer meet the processing requirements of such high-speed data. [0003] The error correction code is a key device to ensure the reliability of the remote sensing satellite data transmission subsystem. At present, the error correction code mainly used in the communication satellite is the 7 / 8 code rate (8176,7154) code recommended by the CCSDS131.1-O-2 s...

AI Technical Summary

Problems solved by technology

However, this design method has several obvious deficiencies: first, the processing flow is complicated, which greatly increases the complexity of coding; second, the introduction of FIFO for data caching not only adds the read and write control logic of FIFO, but also greatly improves the Error probability of data processing during channeling

Third, parallel-to-serial conversion of input data will be introduced, which will introduce cross-clock domain problems, increase the risk of metastable state and unnecessary clock and resource waste; fourth, resource occupation is large, and a large number of FIFO resources are used , and n single-bit serial encoders work at the same time, the logic resources used are at least n times that of single-bit serial encoders

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