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Parallel processing digital filter

A digital filter and parallel processing technology, applied in the direction of digital technology networks, impedance networks, electrical components, etc., can solve the problems of parallel implementation of modules in real-time processing, limiting application and development, etc., to improve throughput and reduce The effect on the probability of state overflow

Inactive Publication Date: 2014-07-30
ZHEJIANG UNIV OF FINANCE & ECONOMICS
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Problems solved by technology

Although the normalized lattice digital filter has a modular structure, it is not implemented in parallel between modules during real-time processing, which limits its application and development to a certain extent

Method used

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Embodiment Construction

[0021] With reference to accompanying drawing, further illustrate the present invention:

[0022] Such as figure 1 As shown, module A of the present invention includes four multipliers, two adders and one delayer. Every time a pulse clock comes, the value in the delayer is used as the signal f k+1 Enter the module of the next level; the signal f from the previous level k and the signal b from the next stage k+1 Respectively with the parameter -sinφ k and cosφ k The multiplication is input to the first adder A1, and the obtained value is stored in the delayer to prepare for the calculation at the next moment; at the same time, the signal f from the previous stage is k and the signal coming from the latter stage b k+1 Respectively with the parameter cosφ k and sinφ k Multiplied and input to the second adder A2, the formed signal b k Prepare for previous level modules.

[0023] Such as figure 2 As shown, the module B of the present invention includes four multipliers,...

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Abstract

The invention discloses a parallel processing digital filter. The parallel processing digital filter is provided with N orders (N is an even number) and comprises N / 2 modularization structures A which comprise four multipliers and two adders, N / 2 modularization structures B which comprise four multipliers and two adders, and N+1 tap coefficients, i.e., N+1 multipliers, wherein a modularization structure A as a first module only comprise two adders and one adder, and the whole apparatus only comprises 5N-1 multipliers and 3N-1 adders; the modularization structures A and the modularization structures B are alternatively cascaded to form a denominator of a filter transfer function; and the series of the tap coefficients and the parameters in all the modules commonly form a numerator of the filter transfer function.

Description

technical field [0001] The invention belongs to the field of digital signal processing, and in particular relates to a digital filter for parallel processing. technical background [0002] Digital filter is one of the most important components in digital signal processing, and is widely used in speech, image processing, digital communication, spectrum analysis, pattern recognition, automatic control and other fields. For practical applications, not only is the digital filter required to be simple in structure, but it must also be robust to finite word length effects, because a well-designed digital filter needs to be realized by dedicated digital devices, and these digital devices with finite word length Often it will greatly degrade the performance of the filter, or even cause its implementation to fail. Therefore, the research and design of efficient and compact digital filters that can effectively resist the finite word length effect has always been a research hotspot fo...

Claims

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Application Information

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IPC IPC(8): H03H17/02
Inventor 黄朝耿周志光林剑
Owner ZHEJIANG UNIV OF FINANCE & ECONOMICS
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