Fabrication method of top metal interconnection layer

Abstract

The invention provides a method for manufacturing top layer metal interconnection layers. The method includes the steps that a semiconductor substrate is provided, a device structure is formed on the semiconductor substrate, and a plurality of bottom layer metal interconnection layers are formed on the device structure; the top layer metal interconnection layers are formed on the multiple bottom layer metal interconnection layers through the electroplating technology, and the grain size of the top layer metal interconnection layers is smaller than 1 micron; next, the chemical and mechanical polishing technology is directly performed on the top layer metal interconnection layers; the top layer metal interconnection layers are covered with passivation layers. Through the method for manufacturing the top layer metal interconnection layers, increase of the grain size of the top layer metal interconnection layers can be avoided, the grain size is controlled to be smaller than 1 micron, and therefore while the wafer conduction test pass percent of semiconductor devices is kept, it is guaranteed that in the chemical and mechanical polishing technology process, the mechanical compressive resistance of the top layer metal interconnection layers is improved, problems such as fracture and collapse occurring to the semiconductor devices are avoided, and the yield of the product is further improved.

Description

technical field [0001] The invention relates to a method for manufacturing a semiconductor device, in particular to a method for manufacturing a top metal interconnection layer. Background technique [0002] In the traditional semiconductor manufacturing process, the top metal interconnect layer (TopMetal) is an indispensable part. With the development of related fields, the requirements for inductance devices are gradually increasing, that is, they need to have a better quality factor Q value, because Reducing the resistivity of the top metal interconnect layer can increase the Q value, and reducing the resistivity of the top metal interconnect layer is generally achieved by thickening the top metal interconnect layer. The thickness of the layer has made higher requirements, and even the top metal interconnection layer with a thickness of 10 μm will be required. [0003] In the prior art, the formation process of the top-level metal interconnection layer usually includes t...

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Problems solved by technology

Usually, after the annealing process, the lattice of the top metal interconnect layer changes, thereby increasing the grain size (GrainSize), and the grain size even reaches 2 μm or more, causing deformation of the semiconductor device, that is, affecting the curvature of the entire wafer, Excessive changes in the curvature of the wafer will affect the mechanical stress of the top metal interconnection layer, resulting in problems such as fracture and collapse of semiconductor devices during the chemical mechanical polishing process

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