Method for making mask layout minimum physical rule verification file

Abstract

The invention discloses a method for manufacturing a mask layout minimum physical rule verification file. The method is implemented in a LINUX system and comprises the steps of manufacturing an EB generating calculation file according to a mask layout design document; utilizing an analyzer to finish analysis on layer operation, and obtaining layer and digital information in the layer operation; storing every line of layer operation information in the EB generating calculation file to a layer general table; analyzing every element of logic operation in the EB generating calculation file, and forming the rule verification file; outputting checking instructions and original layer detection information to the rule verification file, and if the rule verification file is still provided with original layer information, returning and executing the second step until the rule verification file is no longer provided with the original layer information; optimizing the rule verification file logic operation, and merging expression analysis. The mask layout minimum physical rule verification file can be generated automatically through the method, a workload of manufacturing the rule verification file can be saved, and encoding accuracy can be improved.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for making a mask layout minimum physical rule verification file. Background technique [0002] EBslit check is to check whether the mask layer (mask layer) of each layer still meets the basic design rules (minimum width, minimum space) after the Logic Operation (hierarchical logic calculation). Usually, the development process of the mask layout minimum physical rule verification file is as follows: figure 1 As shown, two parts of information are required to be input: A. logic calculation generation formula; B. minimum design rule information; to form the mask layout minimum physical rule verification file. A complete mask layout minimum physical rule verification file mainly includes: physical verification file environment variable establishment part, 2-level input part, logic calculation generation part, design rule part; then add file name, attention point...

AI Technical Summary

Problems solved by technology

In real work, 70% of the development time of engineers is spent on the analysis and input of logic levels and logic operations, and the development cycle (including coding and QA) of the minimum physical rule verification file for the mask layout of a conventional platform is about one week. Traditional The method of making the minimum physical rule verification document of the mask layout is not conducive to shortening the development process, and it is easy to cause development errors caused by engineers' analysis and input errors

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