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Formation method of package structure

A technology of packaging structure and plastic sealing layer, which is applied in the manufacture of electrical components, electrical solid devices, semiconductor/solid devices, etc., can solve the problems of low packaging efficiency and achieve the effects of improving efficiency, reducing area and improving integration

Active Publication Date: 2017-01-11
NANTONG FUJITSU MICROELECTRONICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Existing lead frame packages can only be packaged for a single semiconductor chip and lead frame, and the packaging efficiency is low

Method used

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  • Formation method of package structure
  • Formation method of package structure
  • Formation method of package structure

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Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0023] When encapsulating existing leadframes, please refer to the figure 1 First, the wafer needs to be cut to form semiconductor chips 14 one by one, and then metal wires 17 are formed through a wire bonding process. The metal wires 17 connect the pads 15 on the semiconductor chips 14 with the surrounding pins 16, and finally pass The plastic encapsulation material 18 encapsulates the semiconductor chip 14 and the pin 16. The existing packaging process can only realize the packaging of a single semiconductor chip and pin, and the encapsulation efficiency is low. In addition, the pins 16 are arranged around the semiconductor chip 14, and the pads 15 on the semiconductor chip 14 need to be electrically connected to the surrounding pins 16 through metal wires 17, so that the volume occupied by the entire packaging structure is relatively large. , which is not conducive to the improvement of the integration degree of the packaging structure.

[0024]For this reason, the present...

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Abstract

The invention provides a package structure forming method. The method comprises the steps that a lead frame is provided, wherein the lead frame comprises a first surface and a second surface, and has a number of bearing units in matrix arrangement and medium ribs fixing the bearing units; each bearing unit has a number of discrete pins, and an opening is between adjacent pins; a first plastic seal layer is filled in each opening; a first metal bump is formed on the first surface of each pin; a pre-seal panel is provided; the pre-seal panel comprises a second plastic seal layer; a number of integration units are arranged in the second plastic seal layer; at least one semiconductor chip is arranged in each integration unit; a number of pads are arranged on the surface of each semiconductor chip; a second metal bump is arranged on each pad; a solder layer is formed on each second metal bump; the pre-seal panel is inversely arranged on the first surface of the lead frame; and the second metal bumps on the semiconductor chips and the first metal bumps on the pins are welded together. The package structure provided by the invention has the advantage of improved integration.

Description

technical field [0001] The invention relates to the field of semiconductor packaging, in particular to a method for forming a packaging structure. Background technique [0002] With the development of electronic products such as mobile phones and notebook computers towards miniaturization, portable, ultra-thin, multimedia and low-cost to meet the needs of the public, high-density, high-performance, high-reliability and low-cost packaging forms and their Assembly technology has been rapidly developed. Compared with expensive BGA (BallGrid Array) and other packaging forms, new packaging technologies that have developed rapidly in recent years, such as quad flat no-lead QFN (Quad Flat No-leadPackage) packaging, due to their good thermal and electrical properties , small size, low cost and high productivity and many other advantages have triggered a new revolution in the field of microelectronic packaging technology. [0003] figure 1 It is a structural schematic diagram of a...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/50H01L21/58H01L21/60
CPCH01L24/97H01L2224/48091H01L2924/15788
Inventor 陶玉娟刘培生
Owner NANTONG FUJITSU MICROELECTRONICS
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