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Implementation method and device for extendable throughput rate of SM4 cryptographic algorithm

A technology with high throughput and key expansion, which is applied in the field of information security technology and integrated circuit design, can solve the problems of low throughput of the national secret SM4 algorithm, achieve the effect of reducing key expansion, improving throughput and facilitating operation

Inactive Publication Date: 2014-03-26
北京民芯科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] Aiming at the deficiencies of the prior art, the present invention provides a method and device for realizing the scalable high throughput rate of the national secret SM4 algorithm, which solves the problem of low throughput rate of the national secret SM4 algorithm

Method used

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  • Implementation method and device for extendable throughput rate of SM4 cryptographic algorithm
  • Implementation method and device for extendable throughput rate of SM4 cryptographic algorithm
  • Implementation method and device for extendable throughput rate of SM4 cryptographic algorithm

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Embodiment 1

[0038] The currently used national secret SM4 algorithm generally has a throughput bottleneck problem when processing large data.

[0039] Throughput is usually calculated using the following formula:

[0040] Throughput rate TP=clock frequency f*number of group operation units N*128 / group operation time t;

[0041] It can be seen from the above formula that the determining factors of the throughput rate TP are the clock frequency f, the number of grouping operation units N and the grouping operation time t, and the throughput rate TP can be improved by corresponding changes to each element.

[0042] As shown in Table 1, the element relationship diagram of the throughput rate TP:

[0043] Table 1

[0044]

[0045] The clock frequency f, on the one hand, depends on the process of ASIC (or the performance of FPGA), on the other hand, it depends on the RTL implementation of SM4 (such as improving by inserting registers, ROM-based S-box, etc.).

[0046] The number of grouping ...

Embodiment 2

[0072] The embodiment of the present invention also provides a device for improving the throughput rate of the national secret SM4 algorithm, including: input interface, command FIFO, input data FIFO, SM4 control unit, key expansion unit, grouping operation unit, output data FIFO, output interface ,

[0073] in,

[0074] Described input interface, after processor starts DMA, DMA writes data packet into SM4 module by input interface;

[0075] The command FIFO receives the SM4 module and automatically parses out the command information in the data packet;

[0076] The input data FIFO receives the SM4 module and automatically parses out the data information and key information in the data packet;

[0077] The SM4 control unit reads command information from the command FIFO, and starts the key expansion unit according to the update key field key_updt information in the read command information;

[0078] The key expansion unit performs key expansion according to the key informat...

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Abstract

The invention provides an implementation method and device for the extendable throughput rate of the SM4 cryptographic algorithm, and relates to the field of the information safety technology and the integrated circuit design. The implementation method includes the steps that firstly, a processor packages command information to be processed, data information to be processed and secret key information to be processed according to a predefined format to form a data packet; secondly, the processor starts the DMA, and an SM4 module automatically analyzes the data packet; thirdly, an SM4 control unit reads the command information from the command FIFO, starts a secret key extension unit, conducts secret key extension according to the secret key information sent by the input data FIFO, starts grouping arithmetic units according to grouping work mode field information, and conducts encryption operation or decryption operation on the sent data information; fourthly, writing the encryption operation result or the decryption operation result of the grouping arithmetic units in the output data FIFO, and the DMA reads the encryption operation result or the decryption operation result from the output data FIFO through an output interface. According to the implementation method and device, the extendable throughput rate of the SM4 cryptographic algorithm is improved through the data packet, a dual-bus interface and the parallel processing technology.

Description

technical field [0001] The invention relates to the fields of information security technology and integrated circuit design, in particular to a method and device for realizing a scalable high-throughput rate of the national secret SM4 algorithm. Background technique [0002] With the development of information technology, governments and enterprises have higher and higher requirements for secure communication and data storage. National secret algorithms (such as SM4, etc.) are being widely used in economic, military, administrative and other departments to protect information security. The SM4 National Secret Algorithm is the first commercial cipher block algorithm publicly released in my country. It is a symmetrical block cipher system, and its key length and block length are fixed at 128 bits. [0003] At present, the encryption and decryption devices for secure mobile storage and secure communication on the market are mainly implemented by software. These methods are lo...

Claims

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Application Information

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IPC IPC(8): G06F21/72
CPCG06F21/72
Inventor 冷祥纶俞伟卢鼎何勇
Owner 北京民芯科技有限公司
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