A Global Layout Method for VLSI Standard Cells Based on L1 Norm Model

Abstract

The present invention relates to a global layout method of VLSI standard cells based on the L1 norm model, which belongs to the field of VLSI physical design automation technology. The method first expresses the circuit as a hypergraph, and uses half-circumference length and line length The global placement problem of VLSI standard cells computed and density constrained to be non-smooth is modeled as an L1-norm minimization problem, and then the cells are clustered in the clustering stage using a modified optimal choice clustering algorithm adapted to the L1-norm model , and then in the disintegration stage, the clusters are dissociated using the nonlinear programming global placement method. The method has reasonable layout, high efficiency and practicality, and good layout effect.

Description

technical field [0001] The invention relates to a global layout method of VLSI standard cells based on an L1 norm model, and belongs to the technical field of VLSI physical design automation. Background technique [0002] In the current VLSI layout, the scale of integrated circuits continues to increase and the requirements for technology are getting higher and higher, which puts forward higher requirements for the optimization goals and optimization methods of VLSI layout, and the quality of the layout results directly affects the quality of the entire chip. performance. With the rapid growth of the number of units on a chip, especially the widespread application of millions of gate chips, it poses a huge challenge to the automation of VLSI layout design. Therefore, it is of great significance to seek more efficient and practical integrated circuit layout algorithms. [0003] Algorithms used to solve VLSI placement problems can be divided into the following three categori...

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Problems solved by technology

[0005] However, there are two following problems in the existing global layout methods based on analytical methods: (1) in the global layout process, some approximate models (such as quadratic model, LSE model, Bound2bound model, etc.), so there is a large error in the bus length calculated after the approximation and the bus length of the sum of the half-perimeter line length, which is not a good reflection of the actual line length of the layout, so that the quality of the layout cannot be guaranteed; (2 ) The density constraint function is non-smooth, and the existing layout algorithms that apply density control technology use D b (x,y) for smoothing

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